mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 124

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Signal Description
5.2 Signal Description
Table 5-1 describes debug module signals. All ColdFire debug signals are unidirectional
and related to a rising edge of the processor core’s clock signal. The standard 26-pin debug
connector is shown in Section 5.8, “Motorola-Recommended BDM Pinout.”
Figure 5-2 shows PSTCLK timing with respect to PST and DDATA.
5.3 Real-Time Trace Support
Real-time trace, which defines the dynamic execution path, is a fundamental debug
function. The ColdFire solution is to include a parallel output port providing encoded
processor status and data to an external development system. This port is partitioned into
two 4-bit nibbles: one nibble allows the processor to transmit processor status, (PST), and
the other allows operand data to be displayed (debug data, DDATA). The processor status
Development Serial
Clock (DSCLK)
Development Serial
Input (DSI)
Development Serial
Output (DSO)
Breakpoint (BKPT)
Processor Status
Clock (PSTCLK)
Debug Data
(DDATA[3:0])
Processor Status
(PST[3:0])
5-2
Signal
PST
PSTCLK
or
DDATA
Internally synchronized input. (The logic level on DSCLK is validated if it has the same value on
two consecutive rising CLKIN edges.) Clocks the serial communication port to the debug
module during packet transfers. Maximum frequency is 1/5 the processor status clock
(PSTCLK) speed. At the synchronized rising edge of DSCLK, the data input on DSI is sampled
and DSO changes state.
Internally synchronized input that provides data input for the serial communication port to the
debug module.
Provides serial output communication for debug module responses. DSO is registered
internally.
Input used to request a manual breakpoint. Assertion of BKPT puts the processor into a halted
state after the current instruction completes. Halt status is reflected on processor status signals
(PST[3:0]) as the value 0xF.
Delayed version of the processor clock. Its rising edge appears in the center of valid PST and
DDATA output. See Figure 5-2. PSTCLK indicates when the development system should
sample PST and DDATA values.
These output signals display the register breakpoint status as a default, or optionally, captured
address and operand values. The capturing of data values is controlled by the setting of the
CSR. Additionally, execution of the WDDATA instruction by the processor captures operands
which are displayed on DDATA. These signals are updated each processor cycle.
These output signals report the processor status. Table 5-2 shows the encoding of these
signals. These outputs indicate the current status of the processor pipeline and, as a result, are
not related to the current bus transfer. The PST value is updated each processor cycle.
Table 5-1. Debug Module Signals
Figure 5-2. PSTCLK Timing
MCF5272 User’s Manual
Description
MOTOROLA