mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 25

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Figure
Number
MOTOROLA
8-1
8-2
9-1
9-2
9-3
9-4
9-5
9-6
9-7
9-8
9-9
9-10
9-11
9-12
9-13
9-14
9-15
10-1
10-2
10-3
10-4
10-5
11-1
11-2
11-3
11-4
11-5
11-6
11-7
11-8
11-9
11-10
11-11
11-12
11-13
11-14
11-15
11-16
11-17
11-18
11-19
11-20
11-21
Chip Select Base Registers (CSBRn) ........................................................................... 8-3
SDRAM Controller Signals .......................................................................................... 9-2
54-Pin TSOP SDRAM Pin Definition .......................................................................... 9-3
SDRAM Configuration Register (SDCR) .................................................................... 9-6
SDRAM Timing Register (SDTR) ............................................................................... 9-8
Example Setup Time Violation on SDRAM Data Input during Write....................... 9-13
Timing Refinement with Inverted SDCLK................................................................. 9-13
Timing Refinement with True CAS Latency and Inverted SDCLK........................... 9-14
Timing Refinement with Effective CAS Latency....................................................... 9-14
SDRAM Burst Read, 32-Bit Port, Page Miss, Access = 9-1-1-1 ............................... 9-17
SDRAM Burst Read, 32-Bit Port, Page Hit, Access = 5-1-1-1 .................................. 9-18
SDRAM Burst Write, 32-Bit Port, Page Miss, Access = 7-1-1-1 .............................. 9-19
SDRAM Burst Write, 32-Bit Port, Page Hit, Access = 3-1-1-1 ................................. 9-20
SDRAM Refresh Cycle............................................................................................... 9-21
Enter SDRAM Self-Refresh Mode ............................................................................. 9-22
Exit SDRAM Self-Refresh Mode ............................................................................... 9-23
DMA Mode Register (DMR)...................................................................................... 10-2
DMA Interrupt Register (DIR) ................................................................................... 10-4
DMA Source Address Register (DSAR) .................................................................... 10-6
DMA Destination Address Register (DDAR) ............................................................ 10-6
DMA Byte Count Register (DBCR) ........................................................................... 10-6
Ethernet Block Diagram ............................................................................................. 11-2
Fast Ethernet Module Block Diagram ........................................................................ 11-2
Ethernet Frame Format ............................................................................................... 11-4
Ethernet Address Recognition Flowchart ................................................................... 11-8
Ethernet Control Register (ECR) .............................................................................. 11-12
Interrupt Vector Status Register (IVSR)................................................................... 11-14
RDAR Register ......................................................................................................... 11-15
TDAR Register ......................................................................................................... 11-16
MII Management Frame Register (MMFR) ............................................................. 11-17
FIFO Transmit Start Register (TFSR) ...................................................................... 11-22
Receive Control Register (RCR) .............................................................................. 11-23
Maximum Frame Length Register (MFLR) ............................................................. 11-24
Transmit Control Register (TCR) ............................................................................. 11-25
RAM Perfect Match Address Low (MALR) ............................................................ 11-26
RAM Perfect Match Address High (MAUR) ........................................................... 11-26
Chip Select Option Registers (CSORn)....................................................................... 8-5
EIMR Register ......................................................................................................... 11-14
MII Speed Control Register (MSCR) ...................................................................... 11-18
FIFO Receive Bound Register (FRBR) ................................................................... 11-20
FIFO Receive Start Register (FRSR)....................................................................... 11-20
Transmit FIFO Watermark (TFWR)........................................................................ 11-21
Hash Table High (HTUR)........................................................................................ 11-27
ILLUSTRATIONS
Illustrations
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