mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 331

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
The programming of the P1CR register in the above example is achieved with the following
ColdFire code sequence assuming the equates and init sections include the following:
equates and init:
...
Module_Regs_Addr EQU
P1CR
P1ICR
...
move.l
...
move.w
move.w
The above code segment is an example only.
13.6.2.2 Interrupt Configuration Example
The PnICR registers should be configured according to the specific interrupts, periodic and
aperiodic, required for each port. In addition, the port interrupt enable, (PnICR[IE]) should
be set for each active port prior to receiving interrupts.
Assuming port 1 is configured as in the above example then the following configuration
would enable periodic interrupts on port 1 with only the D channel active.
FSM (port 1 Only)
SCIT MODE (GCI ONLY)
SLAVE MODE
IDL10 MODE
Reserved
Port on
#Module_Regs_Addr, A5
#0x9200,d0
d0,P1CR(A5)
P1CR
0x
Figure 13-35. Port 1 Configuration Register (P1CR)
EQU
EQU
Chapter 13. Physical Layer Interface Controller (PLIC)
15 14 13 12 11 10
1
0
0x00300000 ;address of on-chip registers
0x352
0x35A
9
0
1
0
;offset of P1CR register
;reference register from A5
;port 1 config ON, IDL10, SLAVE, port1 FSM
;msb first on B1 and B2, B1 and B2 disabled
;write to P1CR register
0
2
9
1
8
0
7
0
6
0
0
5
0
4
0
3
0
2
0
0
1
0
Application Examples
GCI ACT (GCI ONLY)
0
0
Reserved
B2 msb First
B1 msb First
B2 Disabled
B1 Disabled
13-35