mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 208

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Solving Timing Issues with SDCR[INV]
The incoming data setup time should be inspected during reads. The active clock edge event
of SDCLK now precedes the MCF5272 internal active clock edge event when (REG = 0).
This behavior is frequency dependent. The two following scenarios are possible:
If the delay between shifted SDCLK and following internal system clock edge is shorter
than the read access time of the SDRAM, data is sampled with the true CAS latency.
Selecting a system clock frequency low enough that the SDCLK-to-CLK delay is long
compared to the SDRAM read access time reduces effective CAS latency by 1 cycle.
9-14
Internal CLK
Internal
• High-speed timing refinement with true CAS latency. See Figure 9-7.
• Low-speed timing refinement with reduced effective CAS latency.
Figure 9-7. Timing Refinement with True CAS Latency and Inverted SDCLK
SDCLK
SDCLK
Data
Data
CLK
Figure 9-8. Timing Refinement with Effective CAS Latency
T
SDCLK_to_CLK
Shifted delay of SDCLK
MCF5272 User’s Manual
- T
CASL = 1
acc
> 0 => effective CAS latency reduced by 1
CASL = 2
T
SDCLK_to_CLK
Shifted delay of SDCLK
- T
acc
< 0 => true CAS latency
Delay SDCLK to CLK
SDRAM read access time
SDRAM read access time
Delay SDCLK to CLK
MOTOROLA