mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 64

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MCF5272 Architecture
A software watchdog timer is also provided for system protection. If programmed, the
timer causes a reset to the MCF5272 if it is not refreshed periodically by software.
1.2.2.4 Power Management
The sleep and stop power management modes reduce power consumption by allowing
software to shut down the core, peripherals, or the whole device during inactive periods. To
reduce power consumption further, software can individually disable internal clocks to the
on-chip peripheral modules. The power-saving modes are described as follows:
1.2.2.5 Parallel Input/Output Ports
The MCF5272 has up to three 16-bit general-purpose parallel ports, each line of which can
be programmed as either an input or output. Some port lines have dedicated pins and others
are shared with other MCF5272 functions. Some outputs have high drive current capability.
1.2.2.6 Interrupt Inputs
The MCF5272 has flexible latched interrupt inputs each of which can generate a separate,
maskable interrupt with programmable interrupt priority level and triggering edge (falling
or rising). Each interrupt has its own interrupt vector.
1.2.3 UART Module
The MCF5272 has two full-duplex UART modules with an on-chip baud rate generator
providing both standard and non-standard baud rates up to 5 Mbps. The module is
functionally equivalent to the MC68681 DUART with enhanced features including 24-byte
Tx and Rx FIFOs. Data formats can be 5, 6, 7, or 8 bits with even, odd, or no parity and up
1-6
• Sleep mode uses interrupt control logic to allow any interrupt condition to wake the
• Stop mode is entered by the disabling of the external clock input and is achieved by
processor. As the MCF5272 is fully static, sleep mode is simply the disabling of the
core’s clock after the current instruction completes. An interrupt from any internal
or external source causes on-chip power management logic to reenable the core’s
clock; execution resumes with the next instruction. This allows rapid return from
power-down state as compared to a dynamic implementation that must perform
power-on reset processing before software can handle the interrupt request. If
interrupts are enabled at the appropriate priority level, program control passes to the
relevant interrupt service routine.
software setting a bit in a control register. Program execution stops after the current
instruction. In stop mode, neither the core nor peripherals are active. The MCF5272
consumes very little power in this mode. To resume normal operation, the external
interrupts cause the power management logic to re-enable the external clock input.
The MCF5272 resumes program execution from where it entered stop mode (if no
interrupt are pending), or starts interrupt exception processing if interrupts are
pending.
MCF5272 User’s Manual
MOTOROLA