mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 221

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
29–20
19–18
17–15
14–13
12–10
Bits
9–8
31
30
7
6
5
RESET Reset. Writing a 1 to this location causes the DMA controller to reset to a condition where no
SRCM
DSTM
Name
DSTT
DSTS
RQM
EN
—
—
—
—
transfers are taking place. EN is cleared, preventing new transfers.
Enable. Controls whether the DMA channel is enabled to perform transfers.
0 DMA transfers are disabled.
1 DMA transfers are enabled. The DMA controller can respond to requests from the peripheral or
Reserved, should be cleared.
Request mode. Determines the request mode of the channel. This must be 11.
00–10 Reserved, do not use.
11 Dual address request mode. Both the DMA source and DMA destination are memory
Reserved, should be cleared.
Destination addressing mode for the channel.
00 Static address mode
01 Increment address mode
1x Reserved, do not use.
Destination addressing type. Used internal to the MCF5272 to qualify the address bits. This value
should be compatible with the CSCRn[TM] value used for external RAM or peripheral device
access.
000 Reserved
001 User data access
010 User code access
011–100 Reserved
101 Supervisor data access
110 Supervisor code access
111 Reserved
Destination data transfer type. The DMA controller buffers data from the source address data
fetches until there are enough bytes to perform a destination data write of the size programmed in
these bits. Thus it is possible to configure source accesses to be byte type and destination
addresses to be line burst type. In this case 16 individual byte reads are performed followed by an
indivisible burst write of four longwords. Longword or line bursts are the most efficient data
transfers.
Reserved, should be cleared.
Reserved, should be cleared.
Source addressing mode of the channel.
0 Static address mode
1 Increment address mode
generates internal requests in dual address mode, so long as the conditions described under
the DMA interrupt flags (see Section 10.3.2, “DMA Interrupt Register (DIR)”) do not prevent
transfers from going ahead.
addresses. The MCF5272 supports only dual-address request mode.
DSTS
00
01
10
11
Table 10-2. DMR Field Descriptions
Longword
Byte
Word
16-byte line burst
Chapter 10. DMA Controller
Data Transfer Type
Description
4
1
2
16. Valid only for SDRAM.
Address Incremented by
DMA Controller Registers
10-3