mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 121

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
4.5.3.2 Access Control Registers (ACR0 and ACR1)
The ACRs define memory reference attributes for two memory regions (one per ACR).
These attributes affect every memory reference using the ACRs or the set of default
attributes contained in the CACR. ACRs are examined for each memory reference not
mapped to the SRAM or ROM module. The supervisor-level ACRs are accessed in the CPU
address space using the MOVEC instruction with an Rc encoding of 0x004 and 0x005.
ACRs can be read and written in BDM mode.
Table 4-9 describes ACRn fields.
Reset
31–24
23–16
Field
R/W
Bits
Bits
I
1–0
15
Rc
31
Name
BAM
Name
BA
EN
CLNF
Base address. Compared with A[31:24]. Eligible addresses that match are assigned the access
control attributes of this register.
Base address mask. Setting a BAM bit masks the corresponding BA bit. Setting low-order BAM bits
can define contiguous regions exceeding 16 Mbytes. BAM can define multiple noncontiguous
regions.
Enable. Enables or disables the other ACRn bits.
0 Access control attributes disabled
1 Access control attributes enabled
BA
Control longword fetch. Controls the size of the memory request the cache issues to the bus
controller for different initial line access offsets.
Figure 4-5. Access Control Register Format (ACRn)
Table 4-8. CACR Field Descriptions (Continued)
24
CLNF
Table 4-9. ACRn Field Descriptions
00
01
1x
23
BAM
Chapter 4. Local Memory
Line
Line
Line
00
Write (R/W by debug module)
ACR0: 0x004; ACR1: 0x005
16
0000_0000_0000_0000
Longword Address Bits
EN
15
Line
Line
Line
01
14
Description
Description
SM
Longword Longword
13
Line
Line
10
12
Longword
—
Line
11
Instruction Cache Overview
7
CM BWE
6
5
4
—
3
WP —
2
4-15
1 0