mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 159

no-image

mcf5272

Manufacturer Part Number
mcf5272
Description
Mcf5272 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mcf5272CVF66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf5272CVF66
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mcf5272CVF66 K75N
Manufacturer:
ST
Quantity:
18
Part Number:
mcf5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf5272CVM66
Manufacturer:
MOT
Quantity:
3
Part Number:
mcf5272CVM66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf5272CVM66
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mcf5272CVM66
0
Company:
Part Number:
mcf5272CVM66
Quantity:
6 000
Part Number:
mcf5272CVM66J
Manufacturer:
NSC
Quantity:
36
Part Number:
mcf5272CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf5272CVM66R2
0
Part Number:
mcf5272NF66K75N
Manufacturer:
MOTOROLA
Quantity:
2
Part Number:
mcf5272VF66
Manufacturer:
HYNIX
Quantity:
19
Part Number:
mcf5272VF66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf5272VF66
Manufacturer:
FREESCALE
Quantity:
20 000
MOTOROLA
Note that the debug module requires the use of the internal bus to perform BDM
commands. In Revision A, if the processor is executing a tight loop that is contained within
a single aligned longword, the processor may never grant the internal bus to the debug
module, for example:
label1: nop
or
label2: bra.w label2
The processor grants the internal bus if these loops are forced across two longwords.
5.7 Processor Status, DDATA Definition
This section specifies the ColdFire processor and debug module’s generation of the
processor status (PST) and debug data (DDATA) output on an instruction basis. In general,
the PST/DDATA output for an instruction is defined as follows:
where the {...} definition is optional operand information defined by the setting of the CSR.
The CSR provides capabilities to display operands based on reference type (read, write, or
both). A PST value {0x8, 0x9, or 0xB} identifies the size and presence of valid data to
follow on the DDATA output {1, 2, or 4 bytes}. Additionally, for certain change-of-flow
branch instructions, CSR[BTB] provides the capability to display the target instruction
address on the DDATA output {2, 3, or 4 bytes} using a PST value of {0x9, 0xA, or 0xB}.
5.7.1 User Instruction Set
Table 5-22 shows the PST/DDATA specification for user-mode instructions. Rn represents
any {Dn, An} register. In this definition, the ‘y’ suffix generally denotes the source and ‘x’
denotes the destination operand. For a given instruction, the optional operand data is
displayed only for those effective addresses referencing memory.The ‘DD’ nomenclature
refers to the DDATA outputs.
Instruction
addq.l
addx.l
addi.l
add.l
add.l
and.l
align4
bra.b label1
align4
Table 5-22. PST/DDATA Specification for User-Mode Instructions
Operand Syntax
#imm,<ea>x
<ea>y,Rx
Dy,<ea>x
<ea>y,Dx
#imm,Dx
Dy,Dx
PST = 0x1, {PST = [0x89B], DDATA= operand}
PST = 0x1, {PST = 0xB, DD = source operand}
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source}, {PST = 0xB, DD = destination}
PST = 0x1
PST = 0x1, {PST = 0xB, DD = source operand}
Chapter 5. Debug Support
PST/DDATA
Processor Status, DDATA Definition
5-37

Related parts for mcf5272