mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 134

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Programming Model
Table 5-9 describes DBR fields.
Table 5-10 describes DBMR fields.
The DBR supports both aligned and misaligned references. Table 5-11 shows relationships
between processor address, access size, and location within the 32-bit data bus.
5.4.6 Program Counter Breakpoint/Mask Registers
The PC breakpoint register (PBR) defines an instruction address for use as part of the
trigger. This register’s contents are compared with the processor’s program counter register
DRc[4–0]
5-12
31–0
31–0
Bits
Bits
Reset
Field
R/W DBR is accessible in supervisor mode as debug control register 0x0E, using the WDEBUG instruction and
Name
Name
Mask
Data
through the BDM port using the
DBMR is accessible in supervisor mode as debug control register 0x0F,using the WDEBUG instruction and
via the BDM port using the
(PBR, PBMR)
31
Figure 5-8. Data Breakpoint/Mask Registers (DBR and DBMR)
Data breakpoint value. Contains the value to be compared with the data value from the processor’s
local bus as a breakpoint trigger.
Data breakpoint mask. The 32-bit mask for the data breakpoint trigger. Clearing a DBR bit allows
the corresponding DBR bit to be compared to the appropriate bit of the processor’s local data bus.
Setting a DBMR bit causes that bit to be ignored.
Table 5-11. Access Size and Operand Data Location
Table 5-10. DBMR Field Descriptions
A[1:0]
Table 5-9. DBR Field Descriptions
00
01
10
11
0x
1x
xx
WDMREG
RDMREG
MCF5272 User’s Manual
command.
Access Size
Data (DBR); Mask (DBMR)
0x0E (DBR), 0x0F (DBMR)
and
Longword
Word
Word
Byte
Byte
Byte
Byte
WDMREG
Uninitialized
Description
Description
commands.
Operand Location
D[31:24]
D[23:16]
D[31:16]
D[15:8]
D[15:0]
D[31:0]
D[7:0]
MOTOROLA
0