mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 349

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Address
MOTOROLA
14.5.2 QSPI Delay Register (QDLYR)
Figure 14-5 shows the QSPI delay register.
Table 14-4 gives QDLYR field descriptions.
Reset
Field
R/W
14–8
Bits
7–0
QSPI_Dout
15
QSPI_CLK
QSPI_Din
QSPI_CS
SPE
Name
15
QCD
SPE
DTL
QMR[CPOL] = 0
QMR[CPHA] = 1
QCR[CONT] = 0
14
Figure 14-4. QSPI Clocking and Data Transfer Example
QSPI enable. When set, the QSPI initiates transfers in master mode by executing commands in
the command RAM. Automatically cleared by the QSPI when a transfer completes.The user can
also clear this bit to abort transfer unless QIR[ABRTL] is set. The recommended method for
aborting transfers is to set QWR[HALT].
QSPILCK Delay. When the DSCK bit in the command RAM, is set this field determines the length
of the delay from assertion of the chip selects to valid QSPI_CLK transition.
Delay after transfer.When the DT bit in the command RAM sets this field determines the length of
delay after the serial transfer.
msb
15
15
Chapter 14. Queued Serial Peripheral Interface (QSPI) Module
A
14
14
Figure 14-5. QSPI Delay Register (QDLYR)
13
13
Table 14-4. QDLYR Field Descriptions
12
12
QCD
11
11
10
10
0000_0100_0000_0100
9
9
MBAR + 0x00A4
8
8
R/W
Description
8
7
7
7
6
6
Chip selects are active low
A = QDLYR[QCD]
B = QDLYR[DTL]
5
5
4
4
3
3
DTL
2
2
Programming Model
1
1
0
0
B
14-11
0