mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 516

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mcf5272

Manufacturer Part Number
mcf5272
Description
Mcf5272 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet

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PLIC Module: IDL and GCI Interface Timing Specifications
Figure 23-18 shows IDL slave timings listed in Table 23-18.
Table 23-19 lists timings for GCI slave mode.
Name
23-22
DOUT[0,1,3]
P30
P31
P32
P33
P34
P35
P38
P39
P40
DFSC[2:3]
DIN[0:3]
FSR[0,1]
DCL[0:1]
FSC input high before the falling edge of DCL0, DCL1 (setup time)
FSC0 input low before the rising edge of DCL0 (deassertion setup time),
FSC1 input low before the rising edge of DCL1 (deassertion setup time)
FSC0 input high after the falling edge of DCL0 (hold time),
FSC1 input high after the falling edge of DCL1 (hold time)
DCL0, DCL1 clock frequency
DCL0, DCL1 pulse width low
DCL0, DCL1 pulse width high
Delay from rising edge of FSC0 to low-z and valid data on DOUT0
Delay from rising edge of FSC1 to low-z and valid data on DOUT1
Delay from rising edge of DFSC2 to low-z and valid data on DOUT1
Delay from rising edge of DFSC3 to low-z and valid data on DOUT1, DOUT3
Delay from rising edge of DCL0 to data valid on DOUT0,
Delay from rising edge of DCL1 to data valid on DOUT1, DOUT3
Delay from rising edge of DCL0 to high-z on DOUT0,
Delay from rising edge of DCL1 to high-Z on DOUT1, DOUT3
P15
Table 23-19. GCI Slave Mode Timing, PLIC Ports 0–3
P16
P17
P20
Figure 23-18. IDL Slave Timing
Characteristic
P25
P21
MCF5272 User’s Manual
P26
P14
P18
P23
P14
P19
Min
25
25
25
45
45
P24
P22
8192
Max
55
55
30
30
30
% of DCL period
% of DCL period
MOTOROLA
Unit
KHz
nS
nS
nS
nS
nS
nS

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