mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 542

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Pin descriptions, ??–19-39
Pipelines
PLIC
Index-4
address bus, 19-18
byte strobes, 19-19
clock, 19-25
data bus, 19-18
dynamic data bus sizing, 19-18
general-purpose I/O ports, 19-23
interrupt request inputs, 19-23
JTAG test access port and BDM debug
operating mode configuration, 19-38
PLI TDM ports, 19-31–19-36
power supply, 19-39
QSPI signals, 19-30–??
RSTI, 19-22
SDRAM
UART0 module signals, 19-24–19-25
USB module signals and PA, 19-25–19-26
instruction fetch, 2-2
operand execution, 2-3
aperiodic status register, 13-24
application examples, 13-33–13-41
automatic echo mode, 13-9
B1 data
B2 data
B-Channel
clock select register, 13-32
clock synthesis, 13-11
D data
D-Channel
D-Channel request register, 13-31
D-Channel status register, 13-30
frame sync synthesis, 13-13
GCI C/I channel
bank selects, 19-22
clock enable, 19-22
column address strobe, 19-22
row address 10, 19-22
row address strobe, 19-22
write enable, 19-22
receive registers, 13-15
transmit registers, 13-17
receive registers, 13-16
transmit registers, 13-17
HDLC encoded data, 13-6
unencoded data, 13-5
receive registers, 13-16
transmit registers, 13-18
HDLC encoded data, 13-7
unencoded data, 13-7
receive registers, 13-28
transmit registers, 13-29
port, 19-36–19-38
MCF5272 User’s Manual
INDEX
Ports
Power management registers, 6-7
Program counter, 2-7
Programming model
Programming models
PST outputs, 5-3
PULSE instruction, 5-3
GCI interrupts aperiodic status, 13-10
GCI monitor channel
GCI/IDL
initialization, 13-34
interrupt configuration
interrupt control, 13-11
introduction, 13-1
local loopback mode, 13-9
loopback control register, 13-20
periodic status registers, 13-22
port configuration
register memory map, 13-14
registers, general, 13-15
remote loopback mode, 13-9
super frame sync generation, 13-12
sync delay registers, 13-32
timing generator, 13-11
parallel input/output, 1-6
PWM, 18-2
QSPI, 14-9
Ethernet, 11-11
instruction cache, 4-12
MAC, 2-8
overview, 2-5
ROM, 4-6
SIM, 6-3
SRAM, 4-2
supervisor, 2-8, 2-8
user, 2-6
transmit status register, 13-29
receive registers, 13-24
transmit abort register, 13-26
transmit registers, 13-25
transmit status register, 13-27
B- and D-Channel
B- and D-Channel bit alignment, 13-5
block, 13-3
D-Channel contention, 13-8
looping modes, 13-8
periodic frame interrupts, 13-10
example, 13-35
registers, 13-21
example, 13-34
registers, 13-19
receive data registers, 13-3
transmit data registers, 13-4
MOTOROLA