mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 533

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
0x0394
0x0398
0x039C
0x08CC
0x0C0C
0x038C
0x084C
0x08D0
0x08EC
0x0C00
0x0C04
0x0C08
0x0C10
0x0C14
0x0C18
0x0C40
0x0DFF
0x08E4
0x0392
0x0840
0x0844
0x0848
0x0850
0x0854
0x0880
0x0884
0x0944
0x0948
0x0984
MBAR
Offset
MBAR
Offset
–
Aperiodic Interrupt Status Register (PASR)
[31:24]
[31:24]
Table A-14. PLIC Module Memory Map (Continued)
Port0 Sync Delay (P0SDR)
Port2 Sync Delay (P2SDR)
Table A-15. Ethernet Module Memory Map
Reserved
Reserved
Appendix A. List of Memory Maps
Ethernet Receive Bound Register (FRBR)
Maximum Frame Length Register (MFLR)
Ethernet Interrupt Mask Register (EIMR)
Ethernet Rx FIFO Start Address (FRSR)
Ethernet Rx Ring Updated Flag (RDAR)
Ethernet Tx FIFO Start Address (TFSR)
Ethernet Tx Ring Updated Flag (TDAR)
Ethernet Interrupt Event Register (EIR)
Ethernet Interrupt Vector Status (IVSR)
Ethernet Rx Descriptor Ring (ERDSR)
Ethernet MII Speed Register (MSCR)
Ethernet Hash Table (Upper) (HTUR)
Ethernet Hash Table (Lower) (HTLR)
Ethernet Tx Descriptor Rin (ETDSR)
Ethernet Rx Control Register (RCR)
Ethernet MII Data Register (MMFR)
Ethernet Tx Control Register (TCR)
[23:16]
[23:16]
Transmit FIFO Watermark (TFWR)
Ethernet Address (Upper) (MAUR)
Ethernet Address (Lower) (MALR)
Ethernet Rx Buffer Size (EMRBR)
Ethernet Control Register (ECR)
FIFO RAM (EFIFO)
Reserved
[15:8]
[15:8]
D Channel Request (PDRQR)
Port1 Sync Delay (P1SDR)
Port3 Sync Delay (P3SDR)
Clock Select (PCSR)
List of Memory Map Tables
Loop back Control
(PLCR)
[7:0]
[7:0]
A-9