mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 23

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
1-1
2-1
2-2
2-3
2-4
2-5
2-6
2-7
2-8
2-9
2-10
3-1
3-2
4-1
4-2
4-3
4-4
4-5
5-1
5-2
5-3
5-4
5-5
5-6
5-7
5-8
5-9
5-10
5-11
5-12
5-13
5-14
5-15
5-16
5-18
5-17
Figure
Number
MCF5272 Block Diagram............................................................................................. 1-2
ColdFire Pipeline .......................................................................................................... 2-2
ColdFire Multiply-Accumulate Functionality Diagram ............................................... 2-4
ColdFire Programming Model...................................................................................... 2-6
Condition Code Register (CCR) ................................................................................... 2-7
Status Register (SR)...................................................................................................... 2-9
Vector Base Register (VBR)......................................................................................... 2-9
Organization of Integer Data Formats in Data Registers............................................ 2-11
Organization of Integer Data Formats in Address Registers ...................................... 2-11
Memory Operand Addressing..................................................................................... 2-12
Exception Stack Frame Form...................................................................................... 2-28
ColdFire MAC Multiplication and Accumulation........................................................ 3-2
MAC Programming Model ........................................................................................... 3-2
SRAM Base Address Register (RAMBAR) ................................................................. 4-3
Instruction Cache Block Diagram................................................................................. 4-8
Cache Control Register (CACR) ................................................................................ 4-13
Access Control Register Format (ACRn) ................................................................... 4-15
Processor/Debug Module Interface............................................................................... 5-1
PSTCLK Timing........................................................................................................... 5-2
Example JMP Instruction Output on PST/DDATA...................................................... 5-5
Debug Programming Model ......................................................................................... 5-6
Address Attribute Trigger Register (AATR) ................................................................ 5-7
Address Breakpoint Registers (ABLR, ABHR) ........................................................... 5-9
Configuration/Status Register (CSR).......................................................................... 5-10
Data Breakpoint/Mask Registers (DBR and DBMR)................................................. 5-12
Program Counter Breakpoint Register (PBR)............................................................. 5-13
Program Counter Breakpoint Mask Register (PBMR) ............................................... 5-13
Trigger Definition Register (TDR) ............................................................................. 5-14
BDM Serial Interface Timing ..................................................................................... 5-17
Receive BDM Packet.................................................................................................. 5-17
Transmit BDM Packet ................................................................................................ 5-18
BDM Command Format ............................................................................................. 5-20
Command Sequence Diagram..................................................................................... 5-21
RAREG
RAREG
ROM Base Address Register (ROMBAR) .................................................................. 4-6
/
/
RDREG
RDREG
Command Sequence............................................................................ 5-22
Command Format ............................................................................... 5-22
ILLUSTRATIONS
Illustrations
Title
Number
Page
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