mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 467

no-image

mcf5272

Manufacturer Part Number
mcf5272
Description
Mcf5272 Coldfire Integrated Microprocessor User
Manufacturer
Freescale Semiconductor, Inc
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
mcf5272CVF66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf5272CVF66
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mcf5272CVF66 K75N
Manufacturer:
ST
Quantity:
18
Part Number:
mcf5272CVF66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf5272CVM66
Manufacturer:
MOT
Quantity:
3
Part Number:
mcf5272CVM66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf5272CVM66
Manufacturer:
FREESCALE
Quantity:
20 000
Part Number:
mcf5272CVM66
0
Company:
Part Number:
mcf5272CVM66
Quantity:
6 000
Part Number:
mcf5272CVM66J
Manufacturer:
NSC
Quantity:
36
Part Number:
mcf5272CVM66J
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf5272CVM66R2
0
Part Number:
mcf5272NF66K75N
Manufacturer:
MOTOROLA
Quantity:
2
Part Number:
mcf5272VF66
Manufacturer:
HYNIX
Quantity:
19
Part Number:
mcf5272VF66
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
Part Number:
mcf5272VF66
Manufacturer:
FREESCALE
Quantity:
20 000
MOTOROLA
20.6.2 Interface for FLASH/SRAM Devices without Byte
CSBRn[EBI] is 11 for FLASH/SRAM devices and for peripherals having 8-bit data bus
widths and no byte strobe inputs. These type of memory devices have separate pins for
write enable, chip select, and output enable. All chip selects support this EBI mode.
The key difference between EBI = 11 and EBI = 00 is that BS[3:0] can be directly
connected to the R/W inputs of the 8-bit wide SRAM devices and the R/W output from the
MCF5272 can be left unconnected.
The number of wait states required for the external memory or peripheral can be
programmed in CSORn[WS]. The external transfer acknowledge signal, TA, is provided to
allow off-chip control of wait states. External control of wait states is enabled when
CSORn[WS] is 0x1F.
SDCLK
A[22:0]
D[31:0]
OE
R/W
CSn
BS[3:0]
TA
Figure 20-10. Longword Read; EBI=11; 32-Bit Port; Internal Termination
Strobes
(H)
(H)
(H)
Chapter 20. Bus Operation
C1
C2
External Bus Interface Types
20-13

Related parts for mcf5272