mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 282

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Register Description and Programming Model
12-22
Bits
14
13
12
11
10
9
8
7
6
5
4
WAKE_CHG
SUSPEND
OUT_EOP
FRM_MAT
OUT_EOT
OUT_LVL
Table 12-14. EP0IMR and EP0ISR Field Descriptions (Continued)
RESUME
IN_EOT
RESET
Name
ASOF
SOF
Frame number match. Set when the USB frame number matches the value written to the
FNMR register.
0 No interrupt pending
1 Frame number match
Artificial start of frame detected. Set when an artificial SOF is generated. The ASOF is
used to notify the user that a SOF packet was not detected as expected.
0 No interrupt pending
1 Artificial SOF generated
Start of frame (SOF) detected. Set when a SOF packet is detected.
0 No interrupt pending
1 SOF detected
Remote wakeup status change interrupt. Indicates that a change has occurred in the
EPSR0[WAKE_ST].
0 No interrupt pending
1 Remote wakeup status bit has changed
Resume. Set when the USB block is in the suspend state and detects resume signaling
on the USB data lines. User-initiated resume signaling also causes the RESUME
interrupt to be asserted.
0 No interrupt pending
1 USB resume signal detected
Suspend. Set when the USB module detects a suspend state on the USB data lines. The
USB suspends when the bus is idle for at least 3 ms.
0 No interrupt pending
1 USB suspend state detected
USB Reset. Set when the USB module detects a USB reset. A USB reset is caused by a
single-ended zero (SE0) greater than 2.5 µs. A USB reset has no effect on the registers
written by the user.
0 No interrupt pending
1 USB reset signal detected
End of transfer. Set when the end of a transfer has been reached for OUT FIFO. An
OUT_EOT is generated when a packet with a size less than the maximum packet size or
the first zero-length packet following maximum size packets is received. The EPDP0 must
be read before clearing this interrupt in order to determine the number of bytes of
remaining data in the FIFO for the last transfer. Any packets received from the host cause
a NAK response until the OUT_EOT interrupt is cleared.
0 No interrupt pending
1 Transfer completed
End of packet. Set when a packet is successfully received for endpoint 0 OUT.
0 No interrupt pending
1 OUT packet received successfully
OUT FIFO threshold level. Indicates that the FIFO level has risen above the level set in
the EPCTL0 register.
0 No interrupt pending
1 OUT FIFO threshold level reached
End of transfer. This bit is set when the end of a transfer has been reached for an IN
endpoint. An EOT interrupt is generated when a packet with a size less than the
maximum packet size or the first zero-length packet following maximum size packets is
sent.
0 No interrupt pending
1 Transfer completed
MCF5272 User’s Manual
Description
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