mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 281

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
Table 12-14 lists field descriptions for the USB endpoint 0 interrupt mask and
general/endpoint 0 interrupt registers.
Reset
Reset
Reset
Reset
31–17
Field
Field
Field VEND_REQ FRM_MAT
Field OUT_EOT
Addr
Bits
R/W
R/W
R/W
R/W
16
15
Figure 12-18. USB Endpoint 0 Interrupt Mask (EP0IMR) and General/Endpoint 0
VEND_REQ
DEV_CFG
31
23
15
7
Name
—
Interrupt bits are reset by writing a 1 to the specified bits.
Writing 0 has no effect.
Table 12-14. EP0IMR and EP0ISR Field Descriptions
OUT_EOP
14
6
Reserved, should be cleared.
Device configuration change interrupt. Set when a device configuration change has been
received. The USB standard device requests SET_CONFIGURATION and
SET_INTERFACE generate a DEV_CFG interrupt. Any IN or OUT packets to the active
endpoints cause a NAK response to the host while this bit is set in order to allow the user
to initialize the endpoints’ FIFO’s. Note that if one of these requests is done repeatedly
and therefore the registers don’t change, a DEV_CFG interrupt is still generated. If debug
mode is enabled, a change in FAR also generates an interrupt.
0 No interrupt pending
1 Device configuration change received
Class or vendor specific request received. Set when a class- or vendor-specific request is
received. When the application detects assertion of VEND_REQ interrupt, it should begin
reading DRR1 and DRR2.
0 No interrupt pending
1 Class or vendor specific request received
MBAR + 0x108C (EP0IMR); MBAR + 0x106C (EP0ISR)
Chapter 12. Universal Serial Bus (USB)
OUT_LVL
ASOF
Interrupt Registers (EP0ISR)
13
5
IN_EOT
SOF
NOTE:
—
12
4
0000_0000
0000_0000
0000_0000
0000_0000
R/W
R/W
R/W
R/W
—
WAKE_CHG
Register Description and Programming Model
IN_EOP
Description
11
3
RESUME
UNHALT
10
2
SUSPEND
HALT
17
9
1
DEV_CFG
RESET
IN_LVL
24
16
8
0
12-21