mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 120

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Instruction Cache Overview
4-14
26–25
23–11
Bits
7–6
4–2
27
24
10
9
8
5
CINVA
DBWE
Name
CFRZ
CEIB
DCM
DWP
—
—
—
—
Cache freeze. Allows the user to freeze the contents of the cache. When CFRZ is asserted line
fetches can be initiated and loaded into the line-fill buffer, but a valid cache entry can not be
overwritten. If a given cache location is invalid, the contents of the line-fill buffer can be written
into the memory array while CFRZ is asserted.
0 Normal operation
1 Freeze valid cache lines
Reserved, should be cleared.
Cache invalidate all. Writing a 1 to this bit initiates entire cache invalidation. Note the caches are
not cleared on power-up or normal reset.
0 No invalidation is performed.
1 Initiate invalidation of the entire cache. The cache controller sequentially clears V in all sets.
Reserved, should be cleared.
Default noncacheable fill buffer. Determines if the fill buffer can store noncacheable accesses
0 Fill buffer not used to store noncacheable instruction accesses (16 or 32 bits).
1 Fill buffer used to store noncacheable accesses. The fill buffer is used only for normal (TT = 0)
Note that this feature can cause a coherency problem for self-modifying code. If CEIB = 1 and a
cache-inhibited access uses the fill buffer, instructions remain valid in the fill buffer until a
cache-invalidate-all instruction, another cache-inhibited burst, or a miss that initiates a fill.
Default cache mode. See Section 4.5.2.3, “Caching Modes.”
0 Default cacheable
1 Default noncacheable
Default buffered write enable. Defines the default value for enabling buffered writes. Generally,
enabled buffered writes provide higher system performance but recovery from access errors can
be more difficult. For the ColdFire CPU, reporting access errors on operand writes is always
imprecise and enabling buffered writes simply further decouples the write instruction from the
signaling of the fault
0 Termination of an operand write cycle on the processor's local bus is delayed until the external
1 A local bus write cycle is terminated immediately and the operation buffered in the bus
Reserved, should be cleared.
Default write protect.
0 Read and write accesses permitted
1 Write accesses not permitted
Reserved, should be cleared.
Subsequent accesses stall until invalidation finishes, at which point, CINVA is automatically
cleared. This operation takes 64 clock cycles.
instruction reads of a noncacheable region. Instructions are loaded into the fill buffer by a burst
access (same as a line fill). They stay in the buffer until they are displaced, so subsequent
accesses may not appear on the external bus.
bus cycle completes.
controller. Operand write cycles are effectively decoupled between the processor's local bus
and the external bus.
Table 4-8. CACR Field Descriptions (Continued)
MCF5272 User’s Manual
Description
MOTOROLA