mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 142

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

Background Debug Mode (BDM)
Table 5-18 describes BDM fields.
5.5.3.1.1 Extension Words as Required
Some commands require extension words for addresses and/or immediate data. Addresses
require two extension words because only absolute long addressing is permitted. Longword
accesses are forcibly longword-aligned and word accesses are forcibly word-aligned.
Immediate data can be 1 or 2 words long. Byte and word data each requires a single
extension word and longword data requires two extension words.
Operands and addresses are transferred most-significant word first. In the following
descriptions of the BDM command set, the optional set of extension words is defined as
address, data, or operand data.
5.5.3.2 Command Sequence Diagrams
The command sequence diagram in Figure 5-16 shows serial bus traffic for commands.
Each bubble represents a 17-bit bus transfer. The top half of each bubble indicates the data
the development system sends to the debug module; the bottom half indicates the debug
module’s response to the previous development system commands. Command and result
transactions overlap to minimize latency.
5-20
15–10 Operation Specifies the command. These values are listed in Table 5-17.
7–6
5–4
2–0
15
Bit
9
8
3
Operand
Register
Name
R/W
Size
A/D
00
0
Operation
Reserved
Direction of operand transfer.
0 Data is written to the CPU or to memory from the development system.
1 The transfer is from the CPU to the development system.
Operand data size for sized operations. Addresses are expressed as 32-bit absolute values.
Note that a command performing a byte-sized memory read leaves the upper 8 bits of the
response data undefined. Referenced data is returned in the lower 8 bits of the response.
00 Byte
01 Word
10 Longword
11 Reserved
Reserved
Address/data. Determines whether the register field specifies a data or address register.
0 Indicates a data register.
1 Indicates an address register.
Contains the register number in commands that operate on processor registers.
Operand Size
Figure 5-15. BDM Command Format
Table 5-18. BDM Field Descriptions
10
Bit Values
8 bits
16 bits
32 bits
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MCF5272 User’s Manual
0
9
Extension Word(s)
R/W
8
7
Op Size
Description
6
0
5
0
4
A/D
3
2
Register
MOTOROLA
0