mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 41

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

MOTOROLA
• Chapter 13, “Physical Layer Interface Controller (PLIC),” provides detailed
• Chapter 14, “Queued Serial Peripheral Interface (QSPI) Module,” provides a
• Chapter 15, “Timer Module,” describes configuration and operation of the four
• Chapter 16, “UART Modules,” describes the use of the universal
• Chapter 17, “General Purpose I/O Module,” describes the operation and
• Chapter 18, “Pulse Width Modulation (PWM) Module,” describes the configuration
• Chapter 19, “Signal Descriptions,” provides a listing and brief description of all the
• Chapter 20, “w Bus Operation,” describes the functioning of the bus for
The USB Specification, Revision 1.1 is a recommended supplement to this chapter.
It can be downloaded from http://www.usb.org. Chapter 2 of this specification,
Terms and Abbreviations, provides definitions of many of the words found here.
information about the MCF5272’s physical layer interface controller, a module
intended to support ISDN applications. The chapter begins with a description of
operation and a series of related block diagrams starting with a high-level overview.
Each successive diagram depicts progressively more internal detail. The chapter
then describes timing generation and the programming model and concludes with
three application examples.
feature-set overview and description of operation, including details of the QSPI’s
internal RAM organization. The chapter concludes with the programming model
and a timing diagram.
general-purpose timer modules, timer 0, 1, 2 and 3.
asynchronous/synchronous receiver/transmitters (UARTs) implemented on the
MCF5272, including example register values for typical configurations.
programming model of the three general purpose I/O (GPIO) ports on the
MCF5272. The chapter details pin assignment, direction-control, and data registers.
and operation of the pulse width modulation (PWM) module. It includes a block
diagram, programming model, and timing diagram.
MCF5272 signals. Specifically, it shows which are inputs or outputs, how they are
multiplexed, and the state of each signal at reset. The first listing is organized by
function, with signals appearing alphabetically within each functional group. This is
followed by a second listing sorted by pin number.
data-transfer operations, error conditions, bus arbitration, and reset operations. It
includes detailed timing diagrams showing signal interaction. Operation of the bus
is defined for transfers initiated by the MCF5272 as a bus master. The MCF5272
does not support external bus masters. Note that Chapter 9, “SDRAM Controller,”
describes DRAM cycles.
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Organization
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