mcf5272 Freescale Semiconductor, Inc, mcf5272 Datasheet - Page 202

• Manufacturer Part Number: mcf5272
• Description: Mcf5272 Coldfire Integrated Microprocessor User
• Manufacturer: Freescale Semiconductor, Inc

SDRAM Registers
9.5.2 SDRAM Timing Register (SDTR)
The SDTR is used to configure SDRAM controller refresh counters for the type of SDRAM
devices used and the number of clocks required for each type of SDRAM access. The reset
value is 0x2115. For lower CPU clock frequencies, precharge and activate times can be
reduced to eliminate up to 2 clock cycles from the read and write accesses. Consult the data
sheets of the SDRAMs being considered.
Table 9-8 describes SDTR fields.
9-8
15–10
Bits
9–8
7–6
5–4
Reset
Write
Addr
R/W
Name
RTP
RC
RP
—
15
Refresh timer prescaler. Determines the number of clock cycles x 16 between refreshes. The
following table describes different recommended prescaler settings for different clock frequencies
including a margin of 1.2 µS. Recommended values are as follows:
Refresh count. Indicates the number of clock cycles spent in refresh state (RC + 5). Refresh occurs
during the first of these clock cycles; the rest of the time is the delay that must occur before the
SDRAM is ready to do anything else.
00 5 cycles
01 6 cycles (default)
10 7 cycles
11 8 cycles
Reserved, should be cleared.
Precharge time. Specifies number of clock cycles taken for a precharge (RP + 1).
00 1 cycle
01 2 cycles (default)
10 3 cycles
11 4 cycles
0010_00
RTP
Figure 9-4. SDRAM Timing Register (SDTR)
111101
101011
011101
010110
000100
Table 9-8. SDTR Field Descriptions
RTP
MCF5272 User’s Manual
10
15.6 µs = 1/f*RTP*16
9
RC
MBAR + 0x0186
01
8
61
43
29
22
R/W
4
Description
7
00
—
6
5 MHz (emulator)
System Clock
5
RP
66 MHz
48 MHz
33 MHz
25 MHz
01
4
3
RCD
01
2
MOTOROLA
1
CLT
01
0