tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 95

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
8 TMUX Registers
Table 95. TMUX_RLS_MODE_CTL, Receive Low-speed Control Parameters (R/W)
Agere Systems Inc.
Address
0x4001B
15:14
Bit
9:7
6:4
13
12
11
10
3
2
1
0
TMUX_J1MONMODE[2:0] Receive J1 Monitor Mode. There are six modes, as
TMUX_J0MONMODE[2:0] Receive J0 Monitor Mode. There are six modes, as
TMUX_RCONCATMODE Receive Concatenation Mode. Control bit, when set to
TMUX_REPRDI_MODE
TMUX_8ORMAJORITY
TMUX_RLSPAROEG
TMUX_SDB1B2SEL
TMUX_SFB1B2SEL
TMUX_RPAIS_INS
TMUX_S1MODE4
(continued)
Name
—
Reserved.
Receive Force Path AIS Insertion. Control bit, when
set to a logic 1, causes the receive low-speed signal to
carry PAIS as well as asserting all AUTO_AIS[1—3]
(pins AC6, AE6, and AD6)
Receive Control Bit for Pointer Justifications. Con-
trol bit, when set to a logic 1, causes the pointer inter-
preter to accept an increment or decrement only if 8 out
of 10 bits are correct; otherwise, it will accept an incre-
ment or decrement based on majority vote only.
Receive Signal Degrade Algorithm Input Selection.
Control bit, when set to a logic 1, causes the B2 errors
to contribute to the signal degrade calculation; other-
wise, the B1 error count is used.
Receive Signal Fail Algorithm Input Selection. Con-
trol bit, when set to a logic, causes the B2 errors to con-
tribute to the signal degrade calculation; otherwise, the
B1 error count is used.
defined in J1 monitor on
defined in
Receive S1 Monitor Mode. Control bit, when set to a
logic 1, causes the most significant nibble of the S1 byte
to be monitored; otherwise, the entire S1 byte is moni-
tored.
Receive Low-speed Parity Odd or Even Generation.
Control bit, when set to a logic 1, forces the output parity
bit to be even; otherwise, the parity is odd.
a logic 1, causes the input pointer interpreter to operate
in concatenation mode. This mode is most likely used in
AU-4 mode; otherwise, three independent pointers are
expected.
Receive Enhanced Path RDI Mode. Control bit, when
set to a logic 1, causes the receive path RDI monitor to
monitor the enhanced (3-bit found in G1[3:1]) value of
path RDI; otherwise, a 1-bit value (G1[3]) is monitored.
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Section 17.5.5 J0 Monitor on page
Function
page
(Table
TMXF28155/51 Super Mapper
377.
3) outputs.
370.
Default
Reset
000
000
00
0
0
0
0
0
0
0
0
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