tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 392

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
17 TMUX Functional Description
The TTOAC channel consists of the following signals:
Table 533. Transmit TOAC Modes
Transmit TOAC—DCC1 through DCC3 Mode. In this mode, DCC bytes 1 to 3 are received serially on the data
pin. The clock rate is 192 kHz. The data bytes are received MSB first, and the sequence of data bytes is DCC1,
DCC2, and DCC3. The data signal is partitioned into frames of 3 bytes. The frame repetition rate is 8 kHz.
Transmit TOAC—DCC4 through DCC12 Mode. In this mode, DCC bytes 4 to 12 are received serially on the data
output. The clock rate is 576 kHz. The data bytes are received MSB first, and the sequence of data bytes is DCC4,
DCC5, DCC6, DCC7, DCC8, DCC9, DCC10, DCC11, and DCC12. The data signal is partitioned into frames of
9 bytes. The frame repetition rate is 8 kHz.
Transmit TOAC—Full TOH Access Mode. In this mode, where TMUX_TTOAC_D13MODE = 0 and
TMUX_TTOAC_D412MODE = 0
into frames of 81 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits that are transmitted/received
most significant bit first. The MSB of the first byte of each frame contains an odd/even parity bit over the 648 bits of
the previous frame. The remaining 7 bits of this byte are not specified.
Bytes shown in
ble bytes in the outgoing frame that can be provisioned from the values on the TOAC channel. There are additional
mode bits described in
cated in bold type below are not specified in the standard, but are available for insertion into the outgoing frame via
the register bit, TMUX_TTOAC_AVAIL
ues of these bytes in the outgoing transmit frame are not related to the values on the TTOAC channel.
Table 534. Transmit Transport Overhead Byte Full Access Mode
392
OH Parity
A data signal received by the TMUX in the transmit direction (TTOACDATA, pin AE2). The data bytes per frame
received depend on the values of TMUX_TTOAC_D13MODE and TMUX_TTOAC_D412MODE. See
below.
A clock signal sourced by the TMUX (TTOACCLK, pin AB6). The clock frequency depends on the values of
TMUX_TTOAC_D13MODE and TMUX_TTOAC_D412MODE. See
An 8 kHz synchronization signal (TTOACSYNC, pin AF3) is sourced by the TMUX. This sync signal is normally
low; during the last clock period of each frame, coincident with the least significant bit of the last byte, the sync
signal is high.
DCC4—DCC12
D10
Full TOH mode
D1
D4
D7
DCC1—DCC3
S1
X
X
X
TOAC Mode
Table 534
D10-2
B1-2
D1-2
D4-2
D7-2
Z1-2
X
X
X
Table 535
summarize the access capabilities of the transmit TOAC. This table describes the possi-
D13MODE Value
TMUX_TTOAC_
D10-3
B1-3
D1-3
D4-3
D7-3
Z1-3
X
X
X
(Table 117 on page113
that must be programmed to allow insertion from the TOAC channel. Bytes indi-
1
0
0
(Table
D11
E1
D2
D5
D8
Z2
X
X
X
117). An X in
(continued)
D412MODE Value
TMUX_TTOAC_
D11-2
E1-2
D2-2
K1-2
D5-2
D8-2
Z2-2
X
X
), the data signal (TTOACDATA, pin AE2) is partitioned
Table 534
X
1
0
D11-3
E1-3
D2-3
K1-3
D5-3
D8-3
Table 533
X
X
X
indicates bytes that are don’t cares; the val-
Data Bytes per
below.
D12
Frame
F1
D3
D6
D9
E2
X
X
X
81
3
9
D12-2
D3-2
D6-2
D9-2
F1-2
K2-2
E2-2
X
X
Agere Systems Inc.
Clock Rate
5.184 MHz
192 kHz
576 kHz
May 2001
Table 533
D12-3
D3-3
D6-3
D9-3
F1-3
K2-3
E2-3
X
X