tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 54

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics
Table 49. Framer—LIU Mode Input Timing Specifications
Table 50. Framer—LIU Mode Output Timing Specifications
5.11 Microprocessor Interface Timing
5.11.1 Synchronous Mode
The synchronous microprocessor interface mode is selected when MPMODE (pin AD17) = 1. Interface timing for
the synchronous mode write cycle is given in
Table
Note:
54
LINETXSYNC[28:1]
LINETXDATA[28:1]
LINERXSYNC[28:1]
LINERXDATA[28:1]
LINETXSYNC29
LINETXDATA29
LINERXSYNC29
LINERXDATA29
Output Name
52.
Input Name
In addition to the MPU_CLK, the VT mapper block also requires TLSC52,TLSSYNC52, RLSC52,
RLSSYNC52 signals to access specific portions of the register map. The user needs to make sure that the
VT_RDY bit is set before VT_MAPPER reads/writes can occur.
Figure 14. Microprocessor Interface Synchronous Write Cycle (MPMODE (Pin AD17) = 1)
(66 MHz MAX)
LINETXCLK[28:1]
LINETXCLK[28:1]
DATA[15:0]
MPCLK
ADDR[9:0]
LINETXCLK29
LINETXCLK29
LINERXCLK[28:1]
LINERXCLK[28:1]
(INPUT)
Reference CLK
LINERXCLK29
LINERXCLK29
ADSN
RWN
CSN
DTN
Reference CLK
tADSNVS
tCSNVS
(continued)
HIGH Z
tWS
tWS
tCLK
Figure 14
T1
Test Conditions
tAIPD
C
C
C
C
L
L
L
L
T2
TBD
TBD
TBD
TBD
Setup Time (t
Min
tWS
tADSNVDTF
= TBD pF
= TBD pF
= TBD pF
= TBD pF
and in
T3
tDTNVPD
Tn – 2 Tn – 1
Table 51
Max
35
35
35
35
S
)
Propagation Delay t
and for the read cycle in
Min
–35
–35
–35
–35
Tn
tAPD
tAPD
tAPD
tAPD
tDTNIPD
Min
Hold Time (t
35
35
35
35
HIGH Z
Max
35
35
35
35
Max
PD
—
—
—
—
H
)
Agere Systems Inc.
Figure 15
Unit
Unit
May 2001
ns
ns
ns
ns
ns
ns
ns
ns
and in
5-7659(F)a