tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 436

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
19 VT/TU Mapper Functional Description
BIP-2 errors and REI-V reception are monitored and counted internally. The performance monitoring reset signal
transfers the count to the holding registers for BIP-2 error count (VT_BIP2ERR_CNT[1—28][11:0];
REI-V count (VT_REI_CNT[1—28][10:0]
ters to 0. When SMPR_SAT_ROLLOVER = 1
value. Otherwise, the counts will roll over. The running count and holding register counts will be forced to 0, if the
SPE mapper is requesting AUTO AIS, VT_LOP[1—28] = 1 (loss of pointer), VT_AIS[1—28] = 1 (VT AIS)
(Table
The V5 byte will be checked for received RFI-V via VT_RFI[1—28] bits
the register after the number of consecutive values programmed in bits VT_RDI_NTIME[3:0]
received. A VT_RFI[1—28] change of state is reported by bit VT_RFI_D[1—28]
DS1 byte synchronous mode, RFI-V = 1 will force DS1 RAI downstream to the framer. Unless the VT_RFI_M mask
bit
When operating in normal RDI-V mode (VT_RX_ERDI_EN[1—28] = 1
byte will be checked for received RDI-V and reported via VT_RDI[1—28] bits
latched to this register after VT_RDI_NTIME[3:0] consecutive values have been received. A VT_RDI[1—28]
change of state is reported via VT_RDI_D[1—28]
is set, VT_RDI_D[1—28] = 1 will generate and cause an interrupt.
When operating in enhanced RDI-V mode (VT_RX_ERDI_EN[1—28] = 0
V5 byte will be checked for received RDI-V and reported via VT_RDI[1—28] bit
latched to this register after VT_ERDI_NTIME[3:0]
5—7) have been received. A VT_ERDI[1—28][2:0] change of state is reported via VT_ERDI_D[1—28] (
Unless the VT_ERDI_M[1—28] mask bit
interrupt.
The V5 byte VT/TU signal label will be monitored and reported to the microprocessor using bits
VT_LAB[1—28][2:0]
values programmed in bits VT_LAB_NTIME[3:0]
bit VT_UNEQ[1—28]
via bit VT_UNEQ_D[1—28]
VT_UNEQ_D[1—28] = 1 will generate an interrupt. VT_UNEQ[1—28] will contribute to automatic AIS generation.
The latched signal label will be compared to the expected signal label. If the expected signal label is 001 or if
VT_UNEQ[1—28] is detected, the detection of PLM-V is disabled. Otherwise, any mismatch is reported to the
microprocessor via bit VT_PLM[1—28]
microprocessor via bit VT_PLM_D[1—28]
VT_PLM_D[1—28] = 1 will generate an interrupt.
19.9.2 Z6/N2 Termination
For SONET applications, the Z6 byte is monitored and presented to the microprocessor using bits
VT_Z6_BYTE[1—28][7:0]
three consecutive consistent bytes are received. N2 is defined for tandem connection applications per
ETS 300 417-1-1 and ITU-T G.707/G.783. Low-order tandem connection is not supported.
19.9.3 Z7/K4 Termination
This termination will support enhanced RDI when bit VT_RX_ERDI_EN[1—28] =
page
VT_ERDI[1—28][2:0]
tive values programmed in register bits VT_ERDI_NTIME[3:0]
reported using bit VT_ERDI_D[1—28]
VT_ERDI_D[1—28] = 1 will generate an interrupt.
436
(Table
168). The Z7/K4[3:1] byte will be monitored and reported to the microprocessor with bits
177) or VT_H4LOMF = 1 (loss of H4 multiframe alignment)
173) is set, VT_RFI_D[1—28] = 1 will generate and cause an interrupt.
(Table
(Table
(Table
(Table
177). New values will be latched to the microprocessor after the number of consecutive
(Table
177). Any change in state of VT_UNEQ[1—28] will be reported to the microprocessor
177). New values will be latched to the microprocessor after the number of consecu-
205) for growth and monitoring purposes only. The Z6 byte is updated to when
169). Unless the VT_UNEQ_M[1—28]
(Table
(Table
(Table
(Table
(Table
169). Unless the VT_ERDI_M[1—28]
(Table
177). Any change in state of VT_PLM[1—28] will be reported to the
207)) for microprocessor read, and resets the running count regis-
173) is set, VT_ERDI_D[1—28] = 1 will generate and cause an
(Table
169). Unless the VT_PLM_M[1—28] mask bit is set
(Table
(Table
67), the internal running counts will hold at their maximum
184) have been received. An all zeros signal label will set
169). Unless the VT_RDI_M[1—28]
(continued)
184) consecutive ERDI-V values (V5 bit 8 and Z7 bits
(Table
(Table
184) have been received. A change of state is
(Table 204, starting on page168
(Table
176).
(Table
(Table 204, starting on page168
(Table
177). New values will be latched into
(Table
(Table
173) mask bit is set,
1(Table 204, starting on
(Table
177). New values will be
169). When operating in the
177). New values will be
173) mask bit is set,
(Table
(Table
Agere Systems Inc.
Table
184) have been
173) mask bit
(Table
May 2001
T able
)), the V5
206), and
)), the
173),
169).