tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 327

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
13 Cross Connect (XC) Registers
Table 464. XC3_MDS3_SRC, XC3 DS3 Source Configuration (R/W)
Table 465. XC_PINS_SRC[1—15], XC1 External I/O TXSYNC Source Configuration (R/W)
Table 466. XC_ALCO_SRC[1—15], XC1 External I/O RXCLK Clock Out Source Configuration (R/W)
Agere Systems Inc.
Address
0x500D4 15:2
0x500ED
0x500EE 15:8
0x500EE
0x500FD
Address
0x500E0
0x500E0
Address
0x500FE 15:8
0x500FE
0x500F0
0x500F0
—
—
—
—
15:8
15:8
1:0
Bit
Bit
7:0
Bit
7:0
XC3_SOURCE_ID[1:0] DS3 Level Connections. This register defines the connec-
[2, 4, . . . 28][7:0]
[1, 3, . . . 29][7:0]
[2, 4, . . . 28][7:0]
[1, 3, . . . 29][7:0]
(SOURCE_ID)
(SOURCE_ID)
(SOURCE_ID)
(SOURCE_ID)
XC_SYNC
XC_SYNC
XC_ALCO
XC_ALCO
Name
Name
Name
—
—
—
Source Identifier for External I/O Pin LINETXSYNC. (Even
channels.) In the LIU mode, these registers must be pro-
grammed the same as XC_PIND_SRC[1—15]
registers; in the system interface mode (CHI, PSB, and framer
only), these registers will be programmed separately to
ensure the system data output properly.
Reserved.
Source Identifier for External I/O Pin LINETXSYNC (Odd
channels).
Note: External I/O has 29 channels.
Source Identifier for External I/O Pin LINERXCLK when
Operating in Low Clock Output Mode. (Either DS1/E1 or
DS2.) For DS1/E1 channels, the programmed value of these
registers should be consistent with those of registers
XC_PIND_SRC[1—15]
data for the same channel always will be routed together;
while for DS2 channels, the value of these registers should
match those of registers XC2_M23_SRC[1—7]
(even channels).
Reserved.
Source Identifier for External I/O Pin LINERXCLK when
Operating in Low Clock Output Mode. (Either DS1/E1 or
DS2.) For DS1/E1 channels, the programmed value of these
registers should be consistent with those of registers
XC_PIND_SRC[1—15]
data for the same channel will always be routed together;
while for DS2 channels, the value of these registers should
match those of registers XC2_M23_SRC[1—7] (odd chan-
nels).
Note: External I/O has 29 channels.
Reserved.
tivity at DS3 level among external I/O, M13, and SPE.
00 = M13 inputs/outputs DS3 through external pins.
01 = M13 and SPE pass data to each other.
10 = SPE inputs/outputs DS3 through external pins and M13
11 = SPE inputs/outputs DS3 through external pins and M13
(continued)
is used as a monitor for the transmit DS3.
is used as a monitor for the receive DS3.
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(Table
(Table
Function
Function
Function
451) to ensure that clock and
451) to ensure that clock and
TMXF28155/51 Super Mapper
(Table
(Table
451)
460)
Default
(invalid)
(invalid)
Default
(invalid)
(invalid)
Default
0x0000
Reset
Reset
Reset
0xFF
0xFF
0xFF
0xFF
0x00
0x00
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