tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 575

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
24 Test-Pattern Generation/Detection Functional Description
24.1 Test-Pattern Generator Introduction
The TPG block is a configurable set of test-pattern generators and monitors for the Super Mapper. For mainte-
nance and troubleshooting operations, TPG feeds one or more T1/E1/DS2 test signals (via data, clock, and FS sig-
nal paths) to the crosspoint switch (XC block). The XC block can redistribute or broadcast these signals to any valid
channel in the framer, external I/O, M13 mapper, DJA, or VT mapper blocks. Similarly, any channel arriving at the
XC may be routed to the test monitor. The TPG can also generate DS3 test signals for use via the M13 and SPE
blocks. Single bit-errors can be detected and counted at each monitor.
The test-pattern generator and associated monitors receive configuration and setup information from the micropro-
cessor control interface. Once the rate and data format are chosen, the test generator outputs are fed to the cross-
point (XC). The crosspoint can map the test signals to any valid DS1/E1/DS2 channel in the device, or to a special
set of test monitor channels in the TPG block (for loopback testing of the test generator/monitor pair). The monitor
waits for the expected test pattern and (after a brief synchronization operation) continually checks the data stream
for bit errors. Optionally, a single data-bit or framing-bit error may be generated via a global SMPR_BER_INSRT
(Table 65, SMPR_GTR, Global Trigger Register (RW) on page66
detectability of such an error as it traverses the crosspoint and other system elements.
Simultaneous testing of DS1, E1, DS2, and DS3 signals is supported (one test channel at each rate plus one idle
channel at DS1). The DL (DS1-ESF data link) and E1 Sa (spare) bit fields are read/writable under software control,
allowing for additional system testing control.
Test monitors can automatically detect/count data-bit errors and detect framing-bit or CRC errors in a pseudoran-
dom test sequence, or loss of frame or loss of sync. The TPG can provide an interrupt to the control system, or it
can be operated in a polled mode.
24.2 Features
24.3 Applications
Agere Systems Inc.
Configurable test-pattern generator: DS1, E1, DS2, and DS3 formats.
Pseudorandom bit sequence (PRBS, also known as pseudonoise or PN sequences) based on maximal-length
feedback shift register sequences; PN codes selectable from the following options: QRSS, PRBS15, PRBS20,
PRBS23, ALT_01, ALL_ONES, USER pattern (16 bits, repeating).
The DS1 and E1 test patterns can be transmitted either unframed or as the payload of a framed signal as defined
in ITU-T Recommendation O.150 (see TPG_FRAMEx signals
Single bit-errors or framing-errors may be injected into any test pattern, under register control.
Any sink or receiving channel may be replaced by a test-pattern monitor, which can detect and count bit errors or
misconfigurations, and/or detect idle conditions or AIS.
Data link (DS1-ESF DL) and SSM (E1 multiframe Sa) fields read/writable.
Supports all Super Mapper modes of operation.
Complies with T1.107, T1.231, T1.403, G.703, G.704, O.150.
Super Mapper self-test, crosspoint verification.
Built-in link and system testing support.
Flexible multicast/broadcast capabilities.
Programmable error insertion.
Idle or test-pattern (DS1 only) generation for each channel.
Idle or test-pattern (DS1 only) bit error or activity monitoring for each channel.
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(Table 507
) control signal, in order to confirm the correct
and
TMXF28155/51 Super Mapper
Table
(continued)
508)).
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