tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 57

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
5 Timing Characteristics
ADDR [19:0] Address is asynchronously passed from the host bus to the internal bus. The address will be avail-
DATA [15:0]
RWN (Input) The read (H) write (L) signal is always high except during a write cycle.
CSN (Input) Chip select is an active-low signal.
DTN (Output) Data transfer acknowledge (active-low). DTN is driven asynchronously based on the arrival of CSN.
ADSN (Input) Address strobe is active-low. ADSN must be a minimum of one MPCLK clock period wide.
DSN (Input) Data strobe is active-low.
Agere Systems Inc.
Figure 16. Microprocessor Interface Asynchronous Write Cycle Description (MPMODE (Pin AC18) = 0)
ADDR[19:0]
DATA[15:0]
(INPUT)
ADSN
RWN
CSN
DSN
DTN
able throughout the entire cycle.
Write data is asynchronously passed from the host bus to the internal bus. Data will be available
throughout the entire cycle.
DTN is driven high until the internal transaction is done. DTN is driven high again when either ADSN
or DSN is deasserted. DTN will become 3-stated when CSN is high.
tAVADSF
HIGH Z
tCSFDTR
tAVDSF
(continued)
tCSFDSF
tRWFDSF
tDVDSF
tDSFDTF
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
tADSRDTR
tDSRRWR
tDSNRAI
tDSRDI
tADSRAI
tAICSR
TMXF28155/51 Super Mapper
tCSRDT3
HIGH Z
5-7661(F).ar.1
57