tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 22

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
3 Pin Information
Table 9. DS3 Port, C-Bit, and Datalink Access
3.3.7 M13 Multiplexer/Demultiplexer Receive Section
Two groups of signals are defined in this section. The first group are reference clocks, used internally in the jitter
attenuation and AIS generation processes. Note that these are typically supplied by free-running crystal oscillators.
The outputs below provide access to the received C-bits and data link bits extracted from the received DS3 frame.
These operate in the same way if the source of the DS3 signal is from an SPE or from the external DS3 port.
Table 10. M13 Multiplexer/Demultiplexer Receive Section
22
AC17
AD16
E10
E18
Pin
E14
E13
E12
Pin
E9
E8
DS2AISCLK
RCBSYNC
DS1XCLK
TCBSYNC
E1XCLK
TCBDATA
Symbol
TDLDATA
TCBCLK
TDLCLK
Symbol
(continued)
Type
Type
—
—
—
—
—
—
—
—
—
Pulldown
Pulldown
Pulldown
Pull down
Pull down
I/O
O
I/O
I
I
I
O
O
O
I
I
E1 Reference Clock. This clock is used as a reference for the jitter
attenuator when it is operating in the E1 mode. It must have a fre-
quency of 2.048 MHz, 32.768 MHz, or 65.536 MHz and a stability of
50 ppm. It is also used to generate an E1 AIS (all ones). May be left
unconnected, or tied to ground, if no E1 options are being used.
DS1 Reference Clock. This clock is used as a reference for the jitter
attenuator when it is operating in the DS1 or the J1 mode. It must
have a frequency of 1.544 MHz, 24.704 MHz, or 49.408 MHz and a
stability of ±32 ppm. This clock signal is also used to generate DS1
AIS signals. May be left unconnected or tied to ground, if not, no DS1
options are being used.
DS2 Reference Clock. A 6.312 MHz ±30 ppm input. In the M23
mode, this clock is used to generate DS2 AIS. May be left uncon-
nected or tied to ground if no DS2 options are being used. Note that
C-bit parity mode does no require a DS2 reference clock.
Receive C-Bit Sync. Ten C-bits are output on RCD after they are
demultiplexed from the received DS3 signal. The RCS output is low,
except during the rising edge of RCD that is used to output C2.
Transmit C-Bit Sync. In the C-bit parity mode, 10 C-bits may
optionally be input for multiplexing into the transmit DS3 frame
through the TCBDATA input. The TCBSYNC output is low, except
during the rising edge of TCBCLK that is used to input C2.
Transmit C-Bit Clock. A gapped clock (nominally 93.983 kHz) for
accepting selected C-bits on input M13_CBDATA.
Transmit C-Bit Data. In the C-bit parity mode, the network require-
ments bit (C2), and the unused C-bits (C4, C5, C6, C16, C17, C18,
C19, C20, and C21) may optionally be input for multiplexing into the
transmit DS3 frame through this input.
Transmit Data Link Clock. A gapped clock (nominally 28.195 kHz)
for accepting path maintenance data link C-bits on input TDLDATA.
Transmit Data Link Data. The path maintenance data link C-bits
(C13, C14, and C15) may optionally be input for multiplexing into the
transmit DS3 frame through this input.
Description
Description
Agere Systems Inc.
May 2001