tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 308

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
12 28-Channel Framer Registers
Table 442. FRM_HCR10, Receive HDLC Channel Register 10 (R/W)
* See
Table 443. FRM_HCR11, Receive HDLC Channel Register 11 (RO)
* See
308
Address*
Address*
0x8HP02
0x8HP03
Table 432
Table 432
for mapping of H and P.
for mapping of H and P .
Bits 11:0 can only be written as the channel is being enabled, (i.e., bit 13 held 0 and is now being
written to 1).
15:4
Bit
7:0
Bit
15
14
13
12
11
10
9
8
3
2
1
0
FRM_HRTHRSH Receive FIFO Threshold Interrupt. A 1 indicates this
FRM_RHC_RESET Receive HDLC Reset. When this bit is 1, the channel is
FRM_MATCH[7:0]
FRM_RTHRSEL
FRM_HRMODE
FRM_RIDLE
FRM_RENABL
FRM_OVR
FRM_EOP
FRM_BYTAL
FRM_RFCS
Name
Name
—
—
—
Reserved. Reads 0.
Receive Channel Idle. A 1 indicates this channel has been
detected as idle.
Receive FIFO Overflow. A 1 indicates this channel’s FIFO
has overflowed.
End of Packet. A 1 indicates an end-of-packet has been
detected on this channel.
channel’s FIFO has exceeded the programmed threshold
value.
held in reset.
Reserved. Must write to 0.
Receive HDLC Enable. When this bit is 0 and written to 1,
the channel is reinitialized (i.e., HDLC searching for open-
ing flag, transparent searching for alignment character if so
programmed) and enabled. When this bit is 1 and written to
0, any current HDLC packet will be aborted and the chan-
nel disabled. Writing the same value as currently pro-
grammed has no effect.
Reserved. Must write to 0.
Receive FIFO Threshold Select. This bit selects which of
the two programmable FIFO threshold values to use for this
channel. (0 selects FRM_HRTHRSH0[9:0]
selects FRM_HRTHRSH1[9:0]
Receive FCS Option. Only valid in HDLC mode. When 1,
this bit indicates the FCS at the end of an HDLC packet
should be removed. A 0 indicates it should kept as part of
the packet.
Receive Channel Mode Select. A 0 indicates the channel
is in HDLC mode. A 1 indicates the channel is in transpar-
ent mode.
Byte Alignment. This bit is only used in transparent mode
(forced to 1 in HDLC mode). A 0 indicates no byte align-
ment is done by the receiver. A 1 indicates that byte align-
ment will be done by the receiver once the
FRM_MATCH[7:0] code is found.
Transparent Mode Pattern Match. Only valid in transpar-
ent mode with byte alignment. These bits indicate the pat-
tern to match to begin receiving transparent data (forced to
ones in HDLC mode).
(continued)
Function
Function
(Table
342)).
(Table
Agere Systems Inc.
341), 1
May 2001
Default
Reset
0x000
Default
Reset
0x0
0
0
0
0
0
0
0
0
0
0
0
0