tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 412

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
18 SPE Mapper Functional Description
Table 536. J1 Monitor
18.14.3 B3 BIP-8 Check
A B3 BIP-8 even parity is computed over all the incoming bits of the TUG-3 frame, after descrambling, and com-
pared to the B3 byte received in the next frame. The total number of B3 BIP-8 bit errors (raw count) or block errors
is counted (selected through SPE_B3BITBLKCNT
internal running counter is placed into SPE_B3ECNT[15:0]
of microprocessor bit SMPR_SAT_ROLLOVER
value until cleared.
18.14.4 Signal Label C2 Byte Monitor
Table 537. STS Signal Label Defect Conditions
412
Any Equipped Functionality
Any Equipped Functionality
Equipped—Nonspecific
Any Payload Specific Code
Any Payload Specific Code
Equipped—Nonspecific (01) or
VT-Structured STS-1 (02)
Any Payload Specific Code
Except VT-Structured
STS-1 (02)
Any Equipped Functionality
Any Equipped Functionality
SPE_J1MONMODE[2:0] = 101: the user will program the 16 expected values of J1 in
SPE_RJ1DEXP[1—16][7:0] in SDH framing mode, where the first byte of the message has the MSB set to 1.
The SPE mapper compares the incoming J1 sequence with the stored expected value, setting the state bit,
SPE_RTIM if they’re different. Any change in state is reported in bit SPE_RTIMD, using interrupt mask bit
SPE_RTIMM.
SPE_J1MONMODE[1:0] = 110 and 111 are currently undefined.
Unless bit PAIS_TIMINH
SPE mapper to the VT mapper).
Unless mask bit SPE_RTIMM is set, bit SPE_RTIMD can generate an interrupt.
Functionality, Expected C2
Provisioned STS PTE
SPE_RJ1DMON[1—64][7:0]
SPE_RJ1DEXP[1—64][7:0]
SPE_J1MONMODE[2:0]
SPE_CNTDJ1[3:0]
SPE_RTIMD
SPE_RTIMM
SPE_RTIM
Name
(Table
(Table
(Table
(Table
(Table
Unequipped (00)
Equipped—Nonspecific (01)
Any Value (02 to E0, FD to FE)
The Same Payload Specific
Code (02 to E0, FD to FE)
A Different Payload Specific
Code (02 to E0, FD to FE)
PDI, 1 to 27 VTx Defects
(E1 to FB)
PDI, 1 to 27 VTx Defects
(E1 to FB)
PDI, 28 VT1.5 Defects or 1
Non-VT Payload Defect (FC)
Reserved (FF)
149) is set, bit SPE_RTIMD contributes to the AUTO AIS control signal from the
(Table
148)
146)
147)
(Table
Received Payload Label
(Table
150)
149)
164)
162)
(C2 in hex)
(Table
(Table
67), the internal counter will roll over or stay at its maximum
(continued)
149)). Upon a performance monitor (PM) interval, the
J1 Monitoring Type.
J1 Expected Data Storage (64/1 Byte).
J1 Received Data Storage (64/1 Byte).
Continuous Times Detect Value.
J1 Mismatch State Bit.
J1 Mismatch Delta Bit, Active-High.
J1 Mismatch Mask Bit, Active-High.
(Table
160) and then cleared. Depending on the value
TMUX_RUNEQP
TMUX_RPLMP
TMUX_RPLMP
Defect
None
None
None
None
None
None
Function
TMUX_FORCEC2DEF = 1
TMUX_RPLMP
TMUX_RPLMP
TMUX_RPLMP
No Change
No Change
No Change
No Change
No Change
No Change
Agere Systems Inc.
(Table
May 2001
97)