tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 56

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
5 Timing Characteristics
MPCLK
ADDR [19:0] The address will be available throughout the entire cycle, and must be stable before ADSN turns
DATA [15:0]
RWN (Input) The read (H) write (L) signal is always high during the read cycle.
CSN (Input) Chip select is an active-low signal.
DTN (Output) Data transfer acknowledge on the host bus interface is initiated on T6. This signal is active for one
ADSN (Input) Address strobe is active-low. ADSN must be one MPCLK clock period wide.
Table 52. Microprocessor Interface Synchronous Read Cycle Specifications
(See Figure 15 on page 55
5.12 Asynchronous Mode
The asynchronous microprocessor interface mode is selected when MPMODE (pin AC18) = 0. Interface timing for
the asynchronous mode write cycle is given in
Table 54
56
t
ADSNVDTF
Symbol
t
t
ADSNSU
t
t
CSNSU
t
SNIPD
t
DAIPD
t
DVPD
t
t
DIPD
APD
CLK
AVS
(see pages 59—60).
16 MHz minimum to 66 MHz maximum frequency.
high.
Read data is stable in Tn –1.
clock and then driven high before entering a high-impedance state. (This is done with an I/O pad
using the input as feedback to qualify the 3-state term.) DT will become 3-stated when CS is high.
Typically DTN is active 4 or 5 MPCLK cycles after ADSN is low.
MPCLK 16 MHz Min—66 MHz Max Frequency
ADDR Valid to MPCLK
MPCLK to ADDR Invalid
CSN Active to MPCLK
ADSN Valid to MPCLK
MPCLK to ADSN Inactive
MPCLK to DTN Valid
MPCLK to DTN Invalid
MPCLK to DATA 3-state
ADSN Valid to DT Falling
for the timing diagram.)
Parameter
(continued)
Figure 16
and in
Table
Setup (ns)
53, and for the read cycle in
(Min)
3.5
3.5
5.5
—
—
—
—
—
—
—
Hold (ns)
(Min)
—
—
—
—
—
0
5
0
0
5
Agere Systems Inc.
Figure 17
Delay (ns)
May 2001
(Max)
1000
—
—
—
—
—
—
8
8
8
and in