tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 206

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
11 M13/M23 MUX/DeMUX Registers
Table 225. M13_DS3_STATUS2, Status (RO)
Table 226. M13_XC_DS2_LOCD_R, DS2 Loss of Clock Delta (RO)
Table 227. M13_XC_DS2_AIS_DETD_R, DS2 Alarm Indication Signal Detection Delta (RO)
206
Address
Address
Address
0x10010 15:7
0x10011 15:7
0x10012 15:7
6:0
6:0
Bit
Bit
Bit
6
5
4
3
2
1
0
M13_RDS3_ALL1_DET This bit is 1 if the input data is 0 for fewer than 9 out of
M13_RDL_FIFO_UF
M13_RDL_FIFO_AF
M13_XC_DS2_
M13_RDS3_LOS
M13_RDS3_LOC
M13_RDS3_SEF
M13_TDS3_LOC
M13_XC_DS2_
AIS_DETD[7:1]
LOCD[7:1]
Name
Name
Name
—
—
—
Reserved.
These individual delta bits are set as the result of the corre-
sponding state bits M13_XC_DS2_LOC[7:1]
tioning either from 0 to 1 or from 1 to 0. They can be
programmed to be either clear on read (COR) or clear on write
(COW), and they are not set to 1 again until the event reoccurs.
This bit is 1 if the SMPR_RDS3CLK signal fails to have tran-
Reserved.
This bit is 1 if the receive HDLC FIFO is underflow.
This bit is 1 if the number of unread bytes in the receive
HDLC FIFO is greater than the fill-up level set by bits
M13_RDL_FILL[1:0]
This bit is 1 if there are three or more F-bit errors in
16 consecutive F bits. It is not terminated until the signal is
in-frame and there are less than three F-bit errors in 16 con-
secutive F bits.
8192 clock periods.
This bit is 1 if there are 175 ±75 contiguous pulse positions
with no pulses of either positive or negative polarity at the
DS3 Input. An LOS is cleared upon detecting an average
pulse density of at least 33% over a period of
175 ±75 contiguous pulse positions, starting with the receipt
of a pulse.
This bit is 1 if the SMPR_TDS3CLK signal fails to have tran-
sitions for at least 10 periods of SMPR_RDS3CLK. A single
transition on SMPR_TDS3CLK resets this bit.
sitions for at least 10 periods of SMPR_TDS3CLK. A single
transition on SMPR_RDS3CLK resets this bit.
Reserved.
These individual delta bits are set as the result of the corre-
sponding state bits M13_XC_DS2_AIS_DET[7:1]
(Table
They can be programmed to be either clear on read (COR)
or clear on write (COW), and they are not set to 1 again until
the event reoccurs.
(continued)
239) transitioning either from 0 to 1 or from 1 to 0.
(Table
Function
Function
Function
287).
(Table
238) transi-
Agere Systems Inc.
May 2001
Default
Default
Default
000000
Reset
0x000
Reset
Reset
0x000
0x00
0x00
000
0
0
1
0
0
0
0