tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 603

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
26 Applications
26.19 HDLC Unit
The HDLC processor formats the HDLC packets for insertion into the programmable channels. A channel can be
any number of bits (1 to 8) from a time slot.
The maximum number of channels is 64. The maximum channel bit rate is 64 kbits/s. The minimum channel bit rate
is 4 kbits/s. Each channels is allocated 128 bytes of storage.
HDLC processing of data on the facility data link (PRMs, Sa bits, or otherwise) is implemented by assigning the
FDL bit position to a logic HDLC channel.
26.20 System Interface
The system interface block provides a programmable interface. It can be configured to work in four different modes.
Agere Systems Inc.
Concentration highway interface (serial time division multiplex interface).
Parallel system bus (parallel time-division multiplex interface/transmit and receive).
Time-division multiplex data rate serial interface.
Network serial multiplexed bus.
— Global frame sync.
— Global clock: 2.048 MHz, 4.096 MHz, 8.192 MHz, or 16.384 MHz.
— 28 transmit and receive data ports; data rates: 2.048 Mbits/s, 4.096 Mbits/s, or 8.192 Mbits/s.
— Global frame sync.
— Global clock: 19 MHz.
— Data rate: 19 MHz.
— 8 bits of data + associated parity bit.
— 4 bits of signaling + 2 bits of signaling control + 1 bit of parity.
— 28 receive frame sync (per port).
— 28 receive clock: 1.544 Mbits/s or 2.048 Mbits/s (per port).
— 28 receive ports.
— One transmit frame sync.
— One transmit clock: 1.544 Mbits/s or 2.048 Mbits/s.
— 28 transmit ports.
— 6- or 8-pin serial interface.
— Transmit and receive clock and data at 51.84 MHz.
— Accommodates 1 DS3 of throughput.
— Provides a minimal pin count interface for data and inverse multiplexing for ATM (IMA) applications without slip
— Three modes of operation: framer—NSMI payload assembled/disassembled into DS1/E1s; M13—proprietary
buffers.
transport format with DS3 framing; SPE—proprietary transport format mapped into an STS-1/AU-3.
(continued)
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
TMXF28155/51 Super Mapper
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