tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 345

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
15 Test-Pattern Generation/Detection Registers
Table 507. TPG_CONFIG0, Register (R/W)
Agere Systems Inc.
Address
0x60030
15:13
Bit
7:6
2:0
12
11
10
9
8
5
4
3
TPM_SEQ0[2:0] These bits select the test pattern to be monitored by the TPG on
TPG_SEQ0[2:0] These Bits Select the Test Pattern to be Generated and
TPM_FRAME0
TPG_FRAME0
TPM_TPINV0
TPG_TPINV0
TPM_EDGE0
TPG_EDGE0
CODE0[1:0]
TPG_FINV0
TPG_TPM_
TPG_TPM_
ESF_0
Name
the DS1 test input.
This bit, if set, inverts the received data for DS1 test signals.
This bit, if set, inverts the transmitted data for DS1 test signals.
This bit, if set, selects the rising edge of XC_TCLK[0] for use as
the retiming clock edge; or else selects falling edge.
This bit, if set, selects the rising edge of TPG_CLK[0] for use as
the transmit clock edge; or else selects falling edge.
This bit selects extended superframe mode for DS1 Test signals.
Don’t Use Line Coding/decoding when 00.
Use HDB3 coding/decoding when 01.
Use B8ZS coding/decoding when 10.
Use AMI coding/decoding when 11.
This code is common to the generator and monitor sides.
This bit is set to select a framed DS1 Test pattern in the monitor.
If this bit is set, the frame bit in the 12th frame of each superframe
is inverted in the DS1 test pattern.
This bit is set to select a framed DS1 test pattern in the genera-
tor.
Transmitted by the TPG on the DS1 Test Output.
000 = PRBS15
001 = PRBS20
010 = QRSS
011 = PRBS23
100 = Alternating
101 = All ones
110 = Unused
111 = User defined
01
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
(continued)
Function
TMXF28155/51 Super Mapper
Default
Reset
000
000
00
0
0
1
1
0
0
0
0
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