tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 437

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
19 VT/TU Mapper Functional Description
The Z7/K4[7:4] byte will be monitored and reported to the microprocessor via bits VT_APS[1—28][3:0]
New values will be latched to the microprocessor after the number of consecutive values programmed in bits
VT_APS_NTIME[3:0]
(Table
interrupt.
19.9.4 Payload Termination
Payload termination will support asynchronous, byte synchronous, and bit synchronous demappings for SONET
VT1.5s and VT2s per Bellcore GR-253 and ANSI T1.105.
Payload termination will support asynchronous, byte synchronous, and bit synchronous demappings for
SDH TU11s and TU12s per ITU-T G.707 and ETS 300 417-4-1.
Demapping modes are selected with bits VT_RX_MAPTYPE[1—28][3:0] (
defined in
Table 555. Receive VT/TU Demapping Selection
The payload termination provides an elastic store for rate adoption. An elastic store overflow is indicated in bit
VT_RX_ESOVFL_D[1—28]
VT_RX_ESOVFL_D[1—28] = 1 will generate an interrupt.
When an overflow condition exists, the read/write count will be forced to the center of the FIFO. The FIFO is 64 bits
deep.
The payload termination circuitry will generate a gapped DS1/E1 clock (VT_TERM_CLK).
on page451
transmitted from the device coincident with the frame bit for DS1 and the MSB of time slot 0 for E1 when demap-
ping a byte synchronous payload.
19.10 Output Signal Selection (OUTSEL)
The OUTSEL logic block (in
DS1/E1 signals with the appropriate AIS clock, data, and frame synchronization.
Agere Systems Inc.
VT_RX_MAPTYPE[1—28][3:0] (See
0
0
0
0
0
0
1
1
1
169). Unless the VT_APS_M[1—28]
Table
describe the DS1 and E1 gapped clocking schemes, respectively. A frame sync is generated and
555.
0
0
0
0
1
1
0
0
0
0110—0111
1011—1111
(Table
(Table
Figure 39 on page429
184) have been received. A change of state is reported using bit VT_APS_D[1—28]
0
0
1
1
0
0
0
0
1
169). Unless the VT_RX_ESOVFL_M[1—28] mask bit is set
Table
(Table
0
1
0
1
0
1
0
1
0
204.)
173) mask bit is set, VT_APS_D[1—28] = 1 will generate an
) will perform all necessary functions to overwrite the outgoing
Asynchronous VT1.5/TU-11 (DS1 output)
Asynchronous VT2/TU-12 (E1 output)
Byte synchronous VT1.5/TU-11 (DS1 output)
Byte synchronous VT2/TU-12 (E1 output)
Bit synchronous VT1.5/TU-11 (DS1 output)
Bit synchronous VT2/TU-12 (E1 output)
Undefined, generates AIS
Asynchronous VT2/TU-12 (DS1 output)
Byte synchronous VT2/TU-12 (DS1 output)
Bit synchronous VT2/TU-12 (DS1 output)
Undefined, generates AIS
(continued)
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Table 204, starting on page168
TMXF28155/51 Super Mapper
Description
Figure 41
(Table
and
(Table
173),
Figure 42
), as
178).
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