tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 455

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tmxf28155

Manufacturer Part Number
tmxf28155
Description
Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
Manufacturer
ETC-unknow
Datasheet

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
tmxf281553BAL3C
Manufacturer:
DSP
Quantity:
5
Preliminary Data Sheet
May 2001
20 M13/M23 MUX/DeMUX Block Functional Description
Contents
20 M13/M23 MUX/DeMUX Block Functional Description .................................................................................... 455
Figures
Figure 47. M13 Block Diagram............................................................................................................................. 457
Figure 48. M12 Functional Block Diagram ........................................................................................................... 458
Figure 49. M23 Functional Block Diagram ........................................................................................................... 459
Figure 50. DS3 NSMI Transmit Operation............................................................................................................ 462
Figure 51. DS3 NSMI Receive Operation............................................................................................................. 462
Tables
Table 575. C-Bit Parity Description and Transmit Value ..................................................................................... 465
Agere Systems Inc.
20.1 M13 Introduction ..................................................................................................................................... 456
20.2 Features ................................................................................................................................................. 456
20.3 Block Diagrams ...................................................................................................................................... 457
20.4 M13 Functional Description .................................................................................................................... 460
20.5 M13 Multiplexing Path ............................................................................................................................ 460
20.6 DS2 Frame Generation .......................................................................................................................... 461
20.7 M23 Multiplexer ...................................................................................................................................... 463
20.8 AIS/Idle Insertion .................................................................................................................................... 467
20.9 B3ZS Encoder (GR-499) ........................................................................................................................ 467
20.10 DS3 R-to-T Loopback ........................................................................................................................... 468
20.11 M13/M23 Demultiplexer ........................................................................................................................ 468
20.2.1 M13 Applications .......................................................................................................................... 456
20.5.1 M12 Multiplexers .......................................................................................................................... 460
20.5.2 DS1/E1 Interface .......................................................................................................................... 460
20.5.3 Loopback Select .......................................................................................................................... 461
20.5.4 DS1/E1 FIFOs .............................................................................................................................. 461
20.6.1 DS1 Mode .................................................................................................................................... 461
20.6.2 E1 Mode ....................................................................................................................................... 462
20.7.1 DS2 Interface ............................................................................................................................... 463
20.7.2 DS2 Select Logic ......................................................................................................................... 463
20.7.3 Overhead Bit Generation (GR-499) ............................................................................................. 463
20.7.4 M23 Mode ................................................................................................................................... 464
20.7.5 C-Bit Parity Mode ......................................................................................................................... 464
20.7.6 FEAC ........................................................................................................................................... 465
20.7.7 FEBE ............................................................................................................................................ 466
20.7.8 Terminal-to-Terminal Path Maintenance Data Link ..................................................................... 466
20.11.2 DS3 T-to-R Loopback ................................................................................................................ 469
20.11.3 M23 Demultiplexer ..................................................................................................................... 469
20.11.4 M12 Demultiplexers ................................................................................................................... 472
20.11.5 DS1 Mode .................................................................................................................................. 472
20.11.6 E1 Mode ..................................................................................................................................... 473
20.11.7 Output Select Logic .................................................................................................................... 474
20.10.1 DS3 Transmit Path Interface ..................................................................................................... 468
20.11.1 DS3 LOC and LOS .................................................................................................................... 468
Table of Contents
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
TMXF28155/51 Super Mapper
Page
Page
Page
455

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