tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 488

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
21.6 Receive Framer Nonalignment Mode (DS1/E1)
In the non-align framing modes the receive frame aligner does not frame to the receive line data. Other than bipolar
violations, AIS, and AUXP monitoring, there is no processing of the receive line data. The entire receive line frame
is given unmodified to the system interface.
21.6.1 Loss of Frame Alignment Criteria
There are two criteria for declaring loss of frame: frame bit errors and CRC errors.
Frame Bit Errors.
10. E1: three consecutive incorrect frame alignment signals or three consecutive incorrect non-FAS frames as indi-
11. E1: 3 consecutive incorrect FAS or non-FAS frames.
12. 2.048 Mbits/s CMI: 2 consecutive missing code rule violations (CRVs).
CRC Errors.
The use of CRC errors to declare loss of frame is optional. CRC errors are monitored in the performance monitor
block.
In DS1 mode, ESF, and J-ESF formats only, N or more CRC-6 errors in a 1 second interval results in loss of frame
alignment. N is provisionable. N defaults to 320 in DS1 mode.
In CEPT mode N, or more, CRC-4 errors in a 1 second interval results in loss of frame alignment. N is provision-
able. N defaults to 915 in CEPT modes.
488
1. T1: two frame bit errors out of 4 frame bits (F
2. T1: two frame bit errors out of 5 frame bits (F
3. T1: two frame bit errors out of 6 frame bits (F
4. T1: three frame bit errors out of 12 frame bits—DDS only (F
5. T1: two frame bit errors out of 4 frame bits (only F
6. T1: two frame bit errors out of 5 frame bits (only F
7. T1: two frame bit errors out of 6 frame bits (only F
8. T1: four frame bit errors out of 12 frame bits—DDS only (F
9. E1: three consecutive incorrect frame alignment signals.
cated by bit 2 in time slot 0 in frames not containing the frame alignment signal.
T
T
T
and F
and F
and F
T
T
T
bits checked).
bits checked).
bits checked).
S
S
S
bits checked).
bits checked).
bits checked).
T
, F
T
, F
S
S
and time slot 24 FAS pattern).
, and time slot 24 F bits).
(continued)
Agere Systems Inc.
May 2001