tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 489

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
21 28-Channel Framer Block Functional Description
21.7 Frame Alignment Criteria
Table 576
Table 576. Frame Alignment Criteria
21.8 Receive and Transmit Signaling Processor
21.8.1 Signaling Introduction and Feature Description
The signaling processor, which is duplicated in the receive and transmit paths, moves signaling data to and from
the following interfaces:
The following frame types are supported when processing signaling to and from the line interface (no special provi-
sioning is needed for the signaling processor to distinguish between these frame types):
Agere Systems Inc.
CEPT CRC-4 100 ms Timer
CEPT CRC-4 400 ms Timer
T1/E1/J1/CMI line interface
System interface
VT mapper interface
Host interface
DS1: ESF; J-ESF; D4; J-D4 (2-, 4-, or 16-state mode)
CEPT Basic Frame; CEPT CRC-4 (100 ms); CEPT CRC-4 (400 ms)
CMI
2.048 Mbits/s CMI Coded
CEPT Basic Frame
ESF and J-ESF
Frame Format
D4 and J-D4
describes the frame alignment criteria for the formats supported by the superframer.
Interface
SLC -96
DDS
SF
Frame alignment is established when six consecutive error-free superframes are
received. Only the F
Frame alignment is established when six consecutive error-free superframes are
received (72 bits checked in D4, 66 bits checked in J-D4).
Frame alignment is established when six consecutive error-free frames are
received (42 bits checked: F
The F
are received (24 F
superframe alignment is established on the first valid F
000111000111. All the while the F
Frame alignment is established when three consecutive error-free superframes are
received (18 bits checked).
Uses the strategy outlined in G.706 paragraph 4.1.2.
Uses the strategy outlined in G.706 paragraphs 4.1.2 and 4.2.
Uses the strategy outlined in G.706 paragraph 4.1.2 and ANNEX B.
Frame alignment is established on the first detection of the CRV violation. Multi-
frame alignment is achieved the first time the 01111111 multiframe alignment pat-
tern is detected.
T
frame position is established when four consecutive error-free superframes
T
bits checked). After establishing the F
T
framing bits are checked (36 bits checked).
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
T
, F
Alignment Procedure
S
, and time slot 24).
T
frame position must remain error free.
(continued)
TMXF28155/51 Super Mapper
S
sequence of
T
frame position, SLC -96
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