tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 547

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
22 Cross Connect (XC) Block Functional Description
The path designations assigned to the framer are consistent with established network definitions. Signals multi-
plexed up into the digital hierarchy from the transmit path. Signals demultiplexed from the digital hierarchy comprise
the receive path.
In switching applications, concentration highway interface (CHI) or parallel system bus (PSB) signals will enter
through the external I/O and are cross connected to the receive system interface (top right side of
signals will traverse the framer through the transmit path frame formatter and are cross connected to the internal
multiplexers/mappers (top left side of
cross connected to the receive path frame aligner (bottom left side of
connected from the transmit system interface to the external I/O pins (bottom right side of
In transport mode, line interface (LIU) signals will enter through the external I/O and are cross connected to the
transmit path frame aligner interface (top right side of
transmit path frame formatter and are cross connected to the internal multiplexers/mappers (top left side of
Figure
frame aligner (bottom left side of
frame formatter to the external I/O pins (bottom right side of
Most applications will cross connect the framer interfaces FRM_TP_T and FRM_RP_R to the M13 MUX or VT
mapper. The framer interfaces FRM_RP_T and FRM_TP_R or the system interfaces FRM_TS and FRM_RS will
be cross connected to the external I/O of the multifunction system interface.
22.3.2 External I/O to Cross Connect Overview
The cross connect defines the connectivity of device pins associated with the DS3 (6 pins), STS-1 POAC (6 pins),
and the multifunction system interface (174 pins). Therefore, the cross connect plays a very large role in configur-
ing the functionality of the Super Mapper from the applications viewpoint.
The multifunction system interface device pins connectivity may be configured to support DS1/E1 (LIU and serial
data/clock/sync), DS2 interfaces, channelized (DS0), and multiplexed system interfaces (CHI, PSB, or NSMI).
Table 610. Multifunction System Interface Programmable I/O
Agere Systems Inc.
LINERXSYNC[1—28]
LINETXSYNC[1—29]
LINERXDATA[1—28]
LINETXDATA[1—29]
LINERXCLK[1—29]
LINETXCLK[1—28]
LINERXDATA[29]
LINERXSYNC29
LINETXCLK[29]
Pin Symbol
82). Signals demultiplexed from DS3 or demapped from SONET are cross connected to the receive path
Input/Output (I/O)
Figure
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
Figure
82) traverse the framer, and are cross connected from the receive path
82). Signals demultiplexed from DS3 or demapped from SONET are
B12, D11, D10, D9, C9, A8, B7, D6, B5, B4, B3, E6, K5, C1, D1, E4,
P24, P23, N26, M25, L23, K23, J23, J24, H26, G25, F23, E25, D25,
C25, F22, A24, A23, D22, B21, A20, C19, D19, B18, B17, B16, A15,
D12, C12, C11, C10, A9, B8, D7, C7, C6, C5, C4, C3, J5, B2, D3,
C13, A12, B11, B10, B9, D8, C8, A7, B6, D5, A4, A3, H5, F5, C2,
R23, P25, N25, M23, M24, L24, K24, J26, H25, G23, G24, F24,
E24, D24, C24, B25, C23, C22, C21, C20, D20, B19, A18, C17,
E23, D26, C26, E21, B24, B23, B22, D21, B20, A19, C18, D18,
R25, P26, N23, N24, M26, L25, K25, J25, H23, H24, G26, F25,
Figure
E3, F3, G3, G4, H2, J1, K3, L3, M3, M4, N2, P2, R4
D2, E2, F4, G2, H1, J3, J4, K4, L4, M2, N1, P4, P3
F2, G1, H3, H4, J2, K2, L2, M1, N3, N4, P1, R2
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Figure
82). The signals will traverse the framer through the
82) on to the LIUs.
D17, D16, B15, A14, T23
Figure
C16, C15, D15, B14
C14, D14, R26
(continued)
82) traverse the framer, and are cross
TMXF28155/51 Super Mapper
D13
A13
R24
Pin
Figure
82).
Figure
82). The
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