tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 467

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
TMXF28155/51 Super Mapper
May 2001
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
20 M13/M23 MUX/DeMUX Block Functional Description
(continued)
FCS Generation. Once the last buffer byte is transmitted, the HDLC controller either transmits a closing flag byte
(when M13_TDL_FCS = 0
(Table
279)), or it first appends the 2-byte ITU-T FCS with the necessary zero stuffing
before sending the closing flag (when M13_TDL_FCS = 1). In either case, the HDLC controller sets
M13_TDL_DONE
(Table
217) to 1 after the transmission of the frame is complete. For testing purposes, the user
can send corrupted FCS bytes by clearing M13_TDL_FCS to 0 and filling the last 2 bytes in the buffer with an incor-
rect CRC value.
LAPD Example. T1.107 defines three standard LAPD messages that may be transmitted on the path maintenance
data link. After the opening flag, each of these messages contains 79 bytes of address, control, and information.
These are followed by the 2-byte FCS and the closing flag.
To transmit one of these messages using the internal HDLC transmitter, the microprocessor should first set
M13_TDL_ACT
(Table
279) to 1, M13_TDL_NTRNL
(Table
279) to 1, and M13_TDL_NTRNL_ACT
(Table
279) to
0. This causes the continuous generation of flag bytes.
The microprocessor may then fill buffer 0 with the first 64 bytes of the message and fill bytes 0 through 14 of buffer
1 with the last 15 bytes prior to the FCS of the message. By setting M13_TDL_BUF0_END (
Table
279) to 0,
M13_TDL_BUF1_END
(Table
279) to 1, and M13_TDL_BYTE_END[5:0]
(Table
280) to 001110, the microproces-
sor can indicate that 79 buffer bytes are to be transmitted.
The microprocessor can then set M13_TDL_FCS to 1 and M13_TDL_NTRNL_ACT to 1. This will cause the inter-
nal HDLC transmitter to send the 79 buffer bytes, append the FCS and closing flag, set M13_TDL_DONE to 1, and
resume continuous flag transmission.
If the same LAPD message is to be transmitted later without first having transmitted a different message, the micro-
processor only needs to toggle M13_TDL_NTRNL_ACT to 0 and back to 1, as the values of the other control
parameters and the buffer bytes are not modified by the internal HDLC transmitter.
20.8 AIS/Idle Insertion
The AIS/idle insertion block can be provisioned to operate in the normal mode (M13_DS3_FORCE_AIS = 0
(Table
276) and M13_DS3_FORCE_IDLE = 0
(Table
276)), generate DS3 AIS (M13_DS3_FORCE_AIS = 1) or
generate DS3 idle (M13_DS3_FORCE_AIS = 0 and M13_DS3_FORCE_IDLE = 1).
In the normal mode, data from the M23 multiplexer is passed unchanged to the B3ZS encoder block.
During AIS insertion (M13_DS3_FORCE_AIS = 1), the generated DS3 frame is altered by overwriting the informa-
tion bits with an alternating 1010 . . . pattern, starting with a 1 after each overhead bit. In addition, the X bits are
overwritten with ones, and the C bits are overwritten with all zeros (T1.107 and T1.404).
During idle signal generation (M13_DS3_FORCE_AIS = 0 and M13_DS3_FORCE_IDLE = 1), the information bits
are overwritten with 11001100 . . ., starting with 11 after each overhead bit. The X bits are overwritten with ones. In
the M23 mode (M13_M23_CBP = 1
(Table
260)), the C bits are overwritten with all zeros. In the C-bit parity mode,
the C bits are passed unchanged (T1.107 and T1.404).
20.9 B3ZS Encoder (GR-499)
The transmit DS3 device output can either be in the form of unipolar data (M13_DS3POS_DATA when
M13_BIPOLAR = 0
(Table
260)) or positive data, and negative data (M13_DS3POS_DATA, and M13_DS3NEG
when M13_BIPOLAR = 1). If M13_BIPOLAR = 1, the DS3 data is B3ZS encoded with M13_DS3POS_DATA = 1
indicating a positive pulse and M13_DS3NEG = 1 indicating a negative pulse.
The B3ZS encoder block accepts data output from the M23 multiplexer and when M13_BIPOLAR = 1, performs
coding as follows: for each input data bit that is a 1, the encoder outputs a 1 (or pulse) on either its positive or neg-
ative output. The positive or negative output is chosen such that the resulting pulse is opposite in polarity to the last
nonzero output.
Agere Systems Inc.
467