tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 67

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

May 2001
7 Microprocessor Interface and Global Control and Status Registers
Table 66. SMPR_MSRR, Block Software Reset Register (RW) (continued)
Agere Systems Inc.
Address
0x0000E
Bit
4
3
2
1
0
SMPR_SPEMPR_SWRS SPEMPR Block Software Reset. When this bit is set
SMPR_VTMPR_SWRS VTMPR Block Software Reset. When this bit is set to 1,
SMPR_TMUX_SWRS
SMPR_M13_SWRS
SMPR_XC_SWRS
Name
XC Block Software Reset. When this bit is set to 1, it will
create a software reset for the cross connect block. This
reset has the same effects as the hardware reset and chip-
level software reset. All microprocessor registers within the
block are reset to their default states. All internal data path
state machine within the block are also reset.
M13 Block Software Reset. When this bit is set to 1, it will
create a software reset for the M13 multiplexer/demulti-
plexer block. This reset has the same effects as the hard-
ware reset and chip-level software reset.
All microprocessor registers within the block are reset to
their default states. All internal data path state machine
within the block are also reset.
it will create a software reset for the VTMPR block. This
reset has the same effects as the hardware reset and
chip-level software reset. All microprocessor registers
within the block are reset to their default states. All inter-
nal data path state machine within the block are also
reset.
to 1, it will create a software reset for the SPEMPR block.
This reset has the same effects as the hardware reset and
chip-level software reset. All microprocessor registers
within the block are reset to their default states. All internal
data path state machine within the block are also reset.
TMUX Block Software Reset. When this bit is set to 1, it
will create a software reset for the TMUX block. This reset
has the same effects as the hardware reset and chip-level
software reset. All microprocessor registers within the
block are reset to their default states. All internal data path
state machine within the block are also reset.
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
Function
(continued)
Default
0x0000
Reset
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