tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 360

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
17 TMUX Functional Description
Contents
Figures
Figure 21. TMUX RTOAC Timing Diagram .......................................................................................................... 362
Figure 22. TMUX TTOAC and RTOAC Timing Diagram ...................................................................................... 365
Figure 23. High-Level TMUX Interconnect ........................................................................................................... 365
Figure 24. Detailed Block Diagram of the TMUX .................................................................................................. 366
Figure 25. Receive Direction Functional Block Diagram ...................................................................................... 367
Figure 26. Pointer Interpretation State Diagram................................................................................................... 374
Figure 27. Receive Low-Speed Bus Interface Signals for STS-3/STM-1 Signals ................................................ 385
Figure 28. Transmit Low-Speed Bus Interface Signals for STS-3/STM-1 Signals ............................................... 386
Figure 29. Transmit Direction POH and TOH Insertion Diagram ......................................................................... 387
Tables
Table 522. Receive TOAC Modes ....................................................................................................................... 373
Table 523. Transport Overhead Byte Access—Receive Direction ...................................................................... 373
Table 524. STS Signal Label Defect Conditions ................................................................................................. 379
Table 525. STS-1 P-REI Interpretation ................................................................................................................ 380
Table 526. Signal Degrade (SD) Parameters ...................................................................................................... 382
Table 527. Signal Fail Parameters ...................................................................................................................... 383
Table 528. Signal Fail or Signal Degrade Recommended Programming Values ................................................ 384
Table 529. Path Overhead Byte Access .............................................................................................................. 384
Table 530. Path Overhead Byte Access—Transmit Direction ............................................................................. 388
Table 531. TPOAC Control Bits ........................................................................................................................... 389
Table 532. RDI-P Defects for Enhanced RDI-P Mode ........................................................................................ 390
Table 533. Transmit TOAC Modes ...................................................................................................................... 392
Table 534. Transmit Transport Overhead Byte Full Access Mode ...................................................................... 392
Table 535. TTOAC Control Bits in Full Access Mode .......................................................................................... 393
360
17.6.19 APS Value and K2 Insert Control Parameters ........................................................................... 393
17.6.20 Criteria for Insert Line RDI ......................................................................................................... 394
17.6.21 Line AIS Generation ................................................................................................................... 394
17.6.22 B2 BIP-8 Calculation and Insert ................................................................................................. 394
17.6.23 F1 Byte Insert ............................................................................................................................. 394
17.6.24 B1 Generate and Error Insert ..................................................................................................... 395
17.6.25 Scrambler ................................................................................................................................... 395
17.6.26 J0 Insert Control ......................................................................................................................... 395
17.6.27 Z0-2, Z0-3 Insert Control ............................................................................................................ 395
17.6.28 A2 Error Insert ............................................................................................................................ 395
Table of Contents
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Agere Systems Inc.
May 2001
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