tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 423

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
18 SPE Mapper Functional Description
18.15.12 N1 Insert Control Parameters
When control bit SPE_TN1INS = 1
N1 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_N1 = 1
default value determined by the microprocessor bit SMPR_OH_DEFLT when SPE_TPOAC_N1 = 0.
18.16 POAC Insert
One overhead access channel (POAC) is provided on-chip to provision the path overhead portion of the outgoing
frame. A POAC channel consists of the following signals:
The data signal is partitioned into frames of 9 bytes. The frame repetition rate is 8 kHz. Each byte consists of 8 bits
that are transmitted/received most significant bit first. The MSB of the second byte of each frame contains an odd/
even parity bit over the 72 bits of the previous frame. The remaining 7 bits of this byte are not specified. The POAC
input has full access to all the path overhead bytes of the STS-1 frame. Bytes shown in the table below summarize
the access capabilities of the transmit POAC channel.
Table 549. Path Overhead Byte Access—Transmit Direction
An event indication is provided to indicate parity errors for the POAC channel. Monitoring of odd or even parity is
selected with bit SPE_TPOAC_OEPMON
SPE_TPOAC_PE
Table 550
predefined default value determined by the value of the microprocessor bit SMPR_OH_DEFLT
inserted on the corresponding POAC value.
Agere Systems Inc.
A 576 kHz inverted clock signal sourced by the SPE mapper (TPOACCLK, pin AE4).
A 576 kbits/s data signal received by the SPE mapper in the transmit direction (TPOACDATA, pin AD5).
An 8 kHz synchronization signal (TPOACSYNC, pin AC5), sourced by the SPE mapper. The sync signal is nor-
mally low; during the first clock period of each frame coincident with the most significant bit of the first byte, the
sync signal is high.
summarizes the insertion options for the specified overhead bytes for POAC. The SPE mapper allows a
(Table
146). The interrupt can be masked with bit SPE_TPOAC_PM
(Table
154), insert the value in SPE_TN1DINS[7:0]
(Table 154 on page143
POH Parity
(continued)
C2
G1
H4
N1
F2
F3
K3
J1
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
). Parity errors are reported with bit
TMXF28155/51 Super Mapper
(Table
(Table 147 on page136
(Table
154) or insert the
157) in the outgoing
(Table
67) to be
423
).