tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 593

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
TMXF28155/51 Super Mapper
May 2001
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
26 Applications
(continued)
26.8.2 Transmit Direction
In the transmit direction, the VT mapper gets a clock, data, and frame sync from the cross connect. The input is
retimed and checked for a digital loss of clock (LOC), an AIS condition, and low zeros-density. In byte-synchronous
mode, the input signal is additionally checked for loss of frame sync (LOFS).
A transmit elastic store synchronizes the incoming DS1/J1/E1 signals to the local STS-1 clock. In asynchronous
and bit-synchronous mode, it works as a bit-oriented (64-bit) FIFO, and in byte-synchronous mode, as a bytewide
(8-byte) buffer using a V5 byte marker bit (8—bit). Overflow or underflow conditions are monitored and reported.
In asynchronous and bit-synchronous mode, a fixed VT pointer of 78 (VT1.5/TU-11) and 105 (VT2/TU-12) is gener-
ated and the payload is mapped into the container using positive/null/negative bit stuffing mechanism (C- and
S bits). In bit-synchronous mode, the bit stuffing mechanism is disabled. In byte-synchronous mode, a dynamic VT
pointer value is generated using the V5 marker implementing NORM, NDF, INC, and DEC pointers.
The VT POH generation comprises V5 byte with BIP2-generation, AIS-, signal label-, UNEQ-insertion, automatic
REI-, RFI-, RDI-, and enhanced RDI-generation ( Bellcore , ITU-T), J2 path trace insertion via microprocessor,
Z6/N2 byte insertion, and Z7/K4 byte insertion via microprocessor or low-order path overhead (LOPOH) access
channel.
The data stream is synchronized to the received 2 kHz sync pulse and multiplexed to form the STS-1/AU-3 signal,
which is then output to the SPE mapper.
When operating in byte-synchronous mode, the phase and signaling bits from the framer are stored and inserted
into the mapped frame.
26.9 M13/M23 Multiplexer
The M13 is a highly configurable multiplexer/demultiplexer. It can operate as an M13 in either the C-bit parity or
M23 mode, a mixed M13/M23, or an M23. In the C-bit parity mode, the M13 provides a far-end alarm and control
(FEAC) code generator and receiver, an HDLC transmitter and receiver, and automatic far-end block error (FEBE)
generation.
Each internal M12 MUX/deMUX and the M23 MUX/deMUX may be configured to operate as independent
MUXs/deMUXs. 28 DS1 inputs in groups of four or 21 E1 input signals in groups of three can feed into individual
M12 MUXs, while the M23 MUX can take DS2 signals from outputs of M12 MUXs, or direct DS2 inputs, or loop-
back deMUXed DS2s.
The M13 supports numerous automatic monitoring functions. It can provide an interrupt to the control system, or it
can be operated in a polled mode.
The M13
complies with T1.102, T1.107, T1.231, T1.403, T1.404, GR-499, G.747, and G.775.
26.9.1 Receive Direction
The receive DS3 is monitored for loss of clock and checked for loss of signal (LOS) according to T1.231. The B3ZS
decoder accepts either unipolar clock and data or unipolar clock, positive and negative data. It also checks for bipo-
lar coding violations. The transmit DS3 can be looped back into the receive side after B3ZS decoding.
The M23 demultiplexer checks for valid DS3 framing by finding the frame alignment pattern (F bits), and then locat-
ing the multi frame alignment signal (M bits). Each M frame, the data stream is checked for the presence of the AIS
(1010) or idle (1100) pattern.
C bits 13, 14, and 15 can be used as a 28.2 kbits/s data link and are available directly at device output via an inter-
nal HDLC receiver. It is composed of a 128-byte FIFO, a CRC-16 frame check sequence (FCS) error detector, and
control circuits.
Agere Systems Inc.
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