tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 498

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
21 28-Channel Framer Block Functional Description
It is possible for the state mode to be implied by the values received on the CHI or PSB bus by the receive system
interface. In this mode, the signaling processor will constantly monitor those values and update the state mode for
each of the time slots on each link.
21.14.2 Signaling State Mode Selection
The signaling state mode is selected by programming bits 5 and 6 in FRM_TSLR0—FRM_TSLR31, Transmit Sig-
naling Link Registers 0—31 (R/W),
isters is illustrated below.
Table 582. Transmit Signaling Link Registers 0—31 Bit Description
The signaling state mode definitions are illustrated in the table below.
Table 583. Transmit Signaling Link Registers 0—31 G-Bit and F-Bit Description
The signaling state mode for DS1 type links should be set to match the function of each time slot. The signaling
state mode does not apply to CEPT type links and the value must be kept in the reset state which is 00. The signal-
ing state mode for CMI type links must be set to 11.
The sixteen state mode, which is the state mode selected out of reset, can be used on SF-type DS1 links in order
to detect a toggle code. In this case, signaling will be collected over two superframes and stored as a 4-bit code.
When programming the state mode for each time slot, the host can also program the DCBA bits in the same regis-
ter. Doing this will determine the default code forwarded to the transmit line or the transmit VT mapper interface
before the first valid signaling code has been extracted from the receive line or receive system interface.
Each of the links and time slots is completely independent from one another with respect to the signaling state
mode selection. Any combination is acceptable.
21.14.3 Signaling Source Selection
There are three sources for signaling in the transmit path.
The signaling source is selected by programming FRM_T_SIGSRC[1:0] in FRM_TSLR32, transmit signaling link
register 32 (R/W),
ing link registers 0—31 must be programmed with valid signaling.
of signaling data in those registers for the different types of links .
498
Transmit Signaling Link Registers 0—31 (host programmed)
Receive System Interface
Receive Line Interface
G and F
Bit 6
G
00
01
10
11
16 state (reset state)
4 state
No signaling
Table 373 on page269
2 state
Bit 5
F
Table 372 on pag e268
Bit 4
—
, bits [1:0]. If the source of signaling is the host, then the transmit signal-
Signaling State Mode Selected
Bit 3
D
for each link. The bit definition for each of those 32 reg-
Table 584 on pag
Bit 2
C
(continued)
e499, shows the organization
Bit 1
B
Agere Systems Inc.
May 2001
Bit 0
A