tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 389

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
17 TMUX Functional Description
An event indication TMUX_TPOAC_PE
page
and is configured with TMUX_TPOAC_OEPMON
Table 531
default value (all zeros or all ones) to be inserted on the corresponding POAC value. All control signals are active-
high.
Table 531. TPOAC Control Bits
17.6.4 AIS Path Generation
Path AIS is specified as all ones in the entire STS-1 signal before scrambling, excluding the transport overhead
(section and line overhead).
Path AIS can be inserted for each STS-1 in the STS-3 using register bits, TMUX_TLS_PAISINS[3:1]
page
17.6.5 J1 Insert Control
A 64-byte sequence stored in TMUX_TJ1DINS[1—3][1—64][7:0]
Table
erwise, the associated POAC value is inserted when TMUX_TPOAC_J1
the default value is inserted when TMUX_TPOAC_J1 is logic 0.
17.6.6 B3 BIP-8 Calculation and Insert
The B3 bytes are allocated for a path overhead error monitoring function. This function will be a bit interleaved par-
ity 8 code (BIP-8) using even parity. The BIP-8 is computed before scrambling over all bits of the previous STS-1
frame except for the first three columns consisting of the section and line overhead and is placed in byte B3 of the
current frame, also before scrambling.
A bit error rate can be inserted on any B3 byte with TMUX_THSB3ERRINS[1—3] (
microprocessor interface block SMPR_BER_INSRT
is asserted, the corresponding B3 byte is inverted each time the SMPR_BER_INSRT bit is asserted.
17.6.7 C2 Signal Label Byte Insert
When TMUX_THSC2INS[1—3] = 1
page
when TMUX_TPOAC_C2 = 1
then the value inserted depends on the microprocessor interface block, SMPR_OH_DEFLT
bit value. If SMPR_OH_DEFLT = 0, then all 0s are inserted. If SMPR_OH_DEFLT = 1, then all ones are inserted.
Agere Systems Inc.
Overhead Bytes
87), is provided to indicate parity errors for the POAC channel. Odd (logic 0)/even (logic 1) parity is checked
102).
118) is inserted into the C2 byte of the outgoing signal. Otherwise, the associated POAC value is inserted
142), will be inserted into the outgoing J1 byte if TMUX_THSJ1INS
summarizes the insertion options for the specified overhead bytes for POAC. The TMUX allows a fixed
C2
K3
N1
F2
F3
J1
TMUX_TPOAC_C2
TMUX_TPOAC_N1
TMUX_TPOAC_F2
TMUX_TPOAC_F3
TMUX_TPOAC_K3
TMUX_TPOAC_J1
(Table 118 on page115
Register Control Bits
(Table 108 on page
(Table 80 on page78
(continued)
(Table
(Table
(Table
(Table
(Table
(Table
(Table 117 on page113
(Table 65 on page
118)
). If both TMUX_THSC2INS and TMUX_TPOAC_C2 = 0,
118)
118)
118)
118)
118)
105), the value in TMUX_TC2INS[1—3][7:0]
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
), interrupt mask bit TMUX_TPOAC_PM
(00000000/11111111)
(Table 140 on page123
SMPR_OH_DEFLT
0 (Default Value)
66) bit. When TMUX_THSB3ERRINS[1—3]
(Table 118 on page
(Table 108 on page105
).
TMXF28155/51 Super Mapper
Table 115 on page112
Values
,
Table
(Table 67 on page68
115) is a logic 1, or
141, and
) is set to 1. Oth-
TPOAC
Data
(Table 124 on
(Table 105 on
1
(Table 84 on
) and
389
)