tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 463

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

Preliminary Data Sheet
May 2001
20 M13/M23 MUX/DeMUX Block Functional Description
20.7 M23 Multiplexer
The M23 multiplexer generates a transmit DS3 frame and fills the information bits in the frame with data either from
the 7 DS2 select blocks when M13_NSMI_MODE = 0
(when M13_NSMI_MODE = 1). It generates the frame using either the SMPR_TDS3CLK or the SMPR_RDS3CLK
input clocks. In the receive loop timing mode (M13_LOOP_TIME = 1
SMPR_RDS3CLK, is selected. Otherwise, SMPR_TDS3CLK is used for DS3 frame generation. SMPR_TDS3CLK
is monitored for loss of clock, which is reported through bit M13_TDS3_LOC
The serial data interface, when enabled (M13_NSMI_MODE = 1), generates a clock M13_NSMI_CLK and an
enable M13_NSMI_EN for accepting DS3 payload data XC_NSMI_DATA. A sync pulse, in reference to and ahead
of the first M bit within a DS3 frame, is also generated. The offset from the sync pulse to the first M bit is program-
mable through bits M13_NSMI_SP_OFFSET[7:0]
The M23 MUX can be provisioned to operate in either the M23 mode (M13_M23_CBP = 1
parity mode (M13_M23_CBP = 0).
An unframed all ones data stream is generated if M13_TDS3_FORCE_ALL1 is set to 1 (
20.7.1 DS2 Interface
The clocks associated with input DS2 signals can be either inputs to the M23 MUX (M13_M23CLK_MODE = 0
(Table
checked for activity or loss of clock (LOC). This is reported to the microprocessor via bits M13_XC_DS2_LOC[7:1]
(Table
(pin E10).
The incoming DS2 data signals (XC_DS2M23DATA[7—1]) are retimed immediately by the associated clocks. The
edge of the clocks that is used to retime the data is user provisionable to either the rising edge
(M13_RDS2_EDGEy = 1
After being retimed, the incoming data stream is checked for AIS. The M13 will declare AIS if the input data is 0 for
fewer than 5 clock cycles in each of two consecutive 840 clock periods. The AIS is not cleared until there are more
than 4 zeros in each of two consecutive 840-bit periods (G.775). If AIS is detected on any of DS2 inputs, the asso-
ciated M13_XC_DS2_AIS_DET[7:1] bit is set
20.7.2 DS2 Select Logic
The selection of DS2 signal source for each DS2 time slot is controlled by M13_AUTO_LB
M13_DS2_LB_DETy
When M13_AUTO_LB = 1 and M13_DS2_LB_DETy = 1, the DS2 signal from time slot y in the received DS3 signal
is looped back into time slot y of the transmitted DS3 signal (see C-Bit Processing on
force a loopback by setting M13_SEL_DS2_LBy to 1. DS2 loopback should not be done in the C-bit parity mode.
If a loopback is not active, the DS2 signal selector is controlled by bits M13_M12_MODEy[1:0]. If register bits
M13_M12_MODEy[1:0] = 00, the output of M12 multiplexer y is chosen for the y
DS3 signal; otherwise, the input DS2 signal XC_DS2M23DATAy is selected for the y
ted DS3 signal.
20.7.3 Overhead Bit Generation (GR-499)
For testing purposes the F bits, M bits, and P bits can be generated with errors. The frame alignment signal (F-bit
pattern that is normally 1001) is generated with the last bit inverted (1000) if M13_DS3_FINV
The multiframe alignment signal (M-bit pattern that is normally 010) is generated as (011) if M13_DS3_MINV
(Table
Agere Systems Inc.
276)) or outputs from the M23 MUX (M13_M23CLK_MODE = 1).The incoming DS2 clock signals are
238). In case LOC is detected, AIS will be inserted into the associated DS2 channel using DS2AISCLK
276) is set.
(Table
(Table
244), M13_SEL_DS2_LBy
283)) or falling edge (M13_RDS2_EDGEy = 0).
(Table
(Table
239).
(Table
(Table
261).
155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
277) or from the serial payload input XC_NSMI_DATA
282), and M13_M12_MODEy
(Table
259)), the received clock,
TMXF28155/51 Super Mapper
(Table
(continued)
th
DS2 time slot in the transmitted
th
225).
page
DS2 time slot in the transmit-
Table
(Table
470). The user can also
(Table
(Table
(Table
276).
260)) or the C-bit
259),
263) bits.
276) is set.
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