tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 422

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
18 SPE Mapper Functional Description
18.15.7 Path RDI (RDI-P) Insert
When transmit RDI software insert control bit SPE_TPRDIINS = 1
(Table
insertion. Each defect contribution to the RDI-P outgoing code can be inhibited. There are two modes supported for
path RDI Insertion. One mode conforms to the earlier 1-bit version of the standard. The other mode, enhanced
RDI-P mode, uses a 3-bit RDI-P code and conforms to the current version of the standard. When the mode selec-
tion bit SPE_TPRDI_MODE = 0
version of the standards. When SPE_TPRDI_MODE = 1, the SPE mapper sends a 3-bit code conforming to the
current enhanced path RDI encoding. Note that for nonenhanced RDI-P mode, the relevant defects are AIS-P and
LOP-P. For enhanced RDI-P mode, the relevant defects are AIS-P, LOP-P, TIM-P, PLM-P, and UNEQ-P,
When a failure condition exists that will cause RDI-P to be generated via hardware, the generation of RDI-P must
last for at least 20 frames before clearing, even if the original failure cause has cleared in less than 20 frames.
The following table describes the encoding of the path-RDI defects.
Table 548. RDI-P Defects for Enhanced RDI-P Mode
18.15.8 F2 Byte Insert
When control bit SPE_TF2INS = 1
F2 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_F2 = 1 (
default value determined by the microprocessor bit SMPR_OH_DEFLT
18.15.9 H4 Insert Control
When control bit SPE_TH4INS = 1 (v), insert the value in SPE_TH4DINS[7:0]
otherwise, insert the associated POAC value when bit SPE_TPOAC_H4 = 1
determined by the microprocessor bit SMPR_OH_DEFLT when SPE_TPOAC_H4 = 0.
18.15.10 F3 Byte Insert
When control bit SPE_TF3INS = 1
F3 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_F3 = 1 (
default value determined by the microprocessor bit SMPR_OH_DEFLT
18.15.11 K3 Insert Control Parameters
When control bit SPE_TK3INS = 1
K3 byte; otherwise, insert the associated POAC value when bit SPE_TPOAC_K3 = 1 (
default value determined by the microprocessor bit SMPR_OH_DEFLT when SPE_TPOAC_K3 = 0.
422
Bit 3
0
0
0
0
1
1
1
1
157) is written into the G1[3:1] output bits. When SPE_TPRDIINS = 0, hardware insert is enabled for RDI-P
Bit 2
G1
0
0
1
1
0
0
1
1
Bit 1
0
1
0
1
0
1
0
1
(Table
(Table
(Table
(Table
155), the SPE mapper sends a 3-bit code that conforms to the earlier 1-bit
154), insert the value in SPE_TF2DINS[7:0]
154), insert the value in SPE_TF3DINS[7:0]
154), insert the value in SPE_TK3DINS[7:0]
LCD-P, PLM-P (LCD-P not supported in Super Mapper)
AIS-P, LOP-P (nonenhanced RDI-P mode)
AIS-P, LOP-P (nonenhanced RDI-P mode)
TIM-P, UNEQ-P (enhanced RDI-P mode)
No defects (nonenhanced RDI-P mode)
No defects (nonenhanced RDI-P mode)
(continued)
AIS-P, LOP-P (enhanced RDI-P mode)
No defects (enhanced RDI-P mode)
(Table
Triggers
(Table
(Table
155), data from SPE_TG1DINS[3:1]
(Table
67) when SPE_TPOAC_F2 = 0.
(Table
67) when SPE_TPOAC_F3 = 0.
154) or insert the default value
157) in the outgoing H4 byte;
Table
Table
(Table
Table
(Table
(Table
154) or insert the
154) or insert the
154) or insert the
157) in the outgoing
157) in the outgoing
157) in the outgoing
Agere Systems Inc.
May 2001
and
TIM-P.