tmxf28155 ETC-unknow, tmxf28155 Datasheet - Page 2

• Manufacturer Part Number: tmxf28155
• Description: Tmxf28155 Super Mapper 155/51 Mbits/s Sonet/sdh X28/x21 Ds1/e1
• Manufacturer: ETC-unknow

155/51 Mbits/s SONET/SDH x28/x21 DS1/E1
1 Features
1.6 M13 Features
1.7 DS3/DS2/DS1/E1 Cross Connect
2
Supports UPSR applications via the dedicated ring
interface and an external tributary selector.
Supports all valid T1/E1/J1 multiplexing structures
into STS-1 and STS-3/STM-1:
Allows grooming of VTs/TUs in granularity of TUG-2s
within the STS-3/STM-1 signal.
Supports J2 trace identifier monitoring/insertion.
Configurable VT/TU slot selection for DS1, E1, and
J1 insertion and drop.
Automatic receive monitor functions include VT/TU
RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V.
Complies with GR-253-CORE, GR-499, ITU-T
G.707, G.704, G.783, T1.105, JT-G707, ETS 300
417-1-1.
Configurable multiplexer/demultiplexer for 28 DS1
signals, 21 E1 signals, or 7 DS2 signals to/from a
DS3 signal.
Operates in either M23 or C-bit parity mode.
Provisionable time slot selection for DS1, E1, and
DS2 insertion or drop.
Full alarm monitoring and generation (LOS, BPV,
EXZ, OOF, SEF, AIS, RAI, FEAC, P-bit and C-bit par-
ity errors, FEBE).
HDLC transmitter with 128-byte data buffer and
HDLC receiver with 128-byte data FIFO for the C-bit
parity path maintenance data link.
DS3, DS2, DS1, and E1 loopback and loopback
request generation.
Complies with T1.102, T1.107, T1.231, T1.403,
T1.404, GR 499, G.747, and G.775.
Highly configurable interconnect for up to 28 DS1 or
21 E1 signals to/from the framer, external pins, M13,
or VT mappers.
Supports up to seven DS2 signals to/from the exter-
nal pins or M13.
— STS-3/STS-1/SPE/VTG/VTx
— STM-1/AU-3/TUG-2/TU-1x/VC-1x
— STM-1/AU-4/TUG-3/TUG-2/TU-1x/VC-1x
(continued)
1.8 Jitter Attenuation
1.9 PDH Interfaces
1.10 T1/E1/J1 Framing Features (x28/x21)
Sources may be broadcast, looped back, or routed
to/from a test-pattern generator or monitor.
Any DS1 or E1 channel may be routed through the
jitter attenuator.
DS3 may be configured for the M13 to interconnect
with the SPE, or external I/O to interconnect with the
M13 or SPE.
PLL-free receive operation using built-in digital jitter
attenuator (in VT/VC mode or M13 mode).
Configurable to meet jitter and MTIE requirements.
One DS3, 7x DS2.
x28/x21 framed or unframed DS1 or E1 interfaces.
One additional dedicated protection channel for
DS2/DS1/E1.
x28/x21 T1/E1/J1 channels.
Line coding: B8ZS, HDB3, ZCS, AMI, and
CMI (JJ20-11).
T1 framing modes: ESF, D4, SLC
and SF (F
E1 framing: G.704 basic and CRC-4 multiframe con-
sistent with G.706.
J1 framing modes: JESF (Japan).
Supports T1 and E1 unframed and transparent trans-
mission format.
T1 signaling modes: transparent;
register and system access for ESF 2-state, 4-state,
and 16-state; D4 2-state, 4-state, and 16-state;
SLC -96 2-state, 4-state, and 16-state; J-ESF han-
dling groups maintenance and signaling; VT 1.5
SPE 2, 4, 16 state.
E1 signaling modes: transparent;
register and system access for entire TS16 multi-
frame structure as per ITU G.732.
Signaling debounce and change of state interrupt.
V5.2 Sa7 processing.
t
only).
®
Agere Systems Inc.
-96, T1 DM DDS,
May 2001